An improved approach to cache management is disclosed which may be implemented to provide fine-grained control over individual caches or subsets of a multi-level cache hierarchy. By selectively operating on shared and unshared caches during power management processing, more efficient system operation can be achieved. In one example, a microprocessor is adapted to interface with multiple caches configured in multiple cache levels. The microprocessor includes multiple processors associated with th...

A processor includes a multi-level cache hierarchy where locality information property such as a Low Locality of Reference (LLR) property is associated with a cache line. The LLR cache line retains the locality information and may move back and forth within the cache hierarchy until evicted from the outer-most level of the cache hierarchy.

A multiple-core processor providing a flexible cache directory scheme. In one embodiment, a processor may include a second-level cache including a number of cache banks and a respective number of cache directories corresponding to the cache banks. The processor may further include a number of processor cores configured to access the cache banks, as well as core/bank mapping logic coupled to the second-level cache and the processor cores. Each of the processor cores may include a respective first...

A multi-processor computer architecture reduces processing time and bus bandwidth during snoop processing. The architecture includes processors and local caches. Each local cache corresponds to one of the processors. The architecture includes one or more virtual busses coupled to the local caches and the processors, and one or more intermediary caches, where at least one intermediary cache is coupled to each virtual bus. Each intermediary cache includes a memory array and means for ensuring the ...

Intermediary inclusive caches (IICs) translate between some number of processors using virtual addressing and a physically addressed bus. The IICs support at least one virtual bus (upper bus) connecting the IICs to central processor units (CPUs), and at least one physical bus (lower bus) connecting the IICs to a memory controller, input/output (I/O) devices and perhaps other IICs. Whenever a CPU makes a request of memory (on the upper bus), the request is looked up in an IIC. Should the data res...

One embodiment of the present invention provides a system that enforces memory-reference ordering requirements at an L2 cache. During operation, the system receives a load at the L2 cache, wherein the load previously caused a miss at an L1cache. Upon receiving the load, the system performs a lookup for the load in reflections of store buffers associated with other L1 caches. These reflections are located at the L2 cache, and each reflection contains addresses for stores in a corresponding store ...

A method and system of enhancing memory performance in a data processing system are provided. The data processing system may include a processor having an on-board first-level cache, a second-level cache coupled to the processor, a system bus coupled to the processor, and a main memory coupled to the system bus. When a memory request is received for a cache line at the first-level cache, a determination is made if the memory request is initiated by a store operation. If the memory request result...

Arrangements and method for enabling and disabling cache bypass in a computer system with a cache hierarchy. Cache bypass status is identified with respect to at least one cache line. A cache line identified as cache bypass enabled is transferred to one or more higher level caches of the cache hierarchy, whereby a next higher level cache in the cache hierarchy is bypassed, while a cache line identified as cache bypass disabled is transferred to one or more higher level caches of the cache hierar...

A prefetching scheme to detect when a load misses the lower level cache and hits the next level cache. Consequently, the prefetching scheme utilizes the previous information for the cache miss to the lower level cache and hit to the next higher level of cache memory that may result in initiating a sidedoor prefetch load for fetching the previous or next cache line into the lower level cache. In order to generate an address for the sidedoor prefetch, a history of cache access is maintained in a q...

A system and method for managing data includes executing a set of instructions which are used for operating on compressed data and another set of instructions (e.g., different instructions) which are used for operating on uncompressed data.