An apparatus includes a central processing unit having an output to provide a status indicator, a graphics controller having an output coupleable to a display interface, a cache comprising a plurality of cache lines, and memory controller having an input to receive the status indicator. The memory controller is configured to disable allocation of cache lines of the cache for cache misses for data requests from the graphics controller in response to the status indicator indicating the central pro...

Avoiding cache-line sharing in virtual machines can be implemented in a system running a host and multiple guest operating systems. The host facilitates hardware access by a guest operating system and oversees memory access by the guest. Because cache lines are associated with memory pages that are spaced at regular intervals, the host can direct guest memory access to only select memory pages, and thereby restrict guest cache use to one or more cache lines. Other guests can be restricted to dif...

A chip multithreading processor schedules and assigns threads to its processing cores dependent on estimated miss rates in a shared cache memory of the threads. A cache miss rate of a thread is estimated by measuring cache miss rates of one or more groups of executing threads, where at least one of the groups includes the thread of interest. Using a determined estimated cache miss rate of the thread, the thread is scheduled with other threads to achieve a relatively low cache miss rate in the sh...

A system, apparatus and method enabling common memory pool tests to be conducted in a multiprocessing system by using substantially the same system components that are used during a normal mode of operation. Under normal mode of operation, a data cache interface facilitates data transfer between processors of a multiprocessor system and the common memory pool. In test mode of operation, an integrated data cache exerciser assumes control of the data cache interface to facilitate test data write a...

A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

In a multiprocessor write-into-cache data processing system including: a memory; at least first and second shared caches; a system bus coupling the memory and the shared caches; at least one processor having a private cache coupled, respectively, to each shared cache; method and apparatus for preventing hogging of ownership of a gateword stored in the memory which governs access to common code/data shared by processes running in the processors by which a read copy of the gateword is obtained by ...

A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into a cache, the cache is marked as containing an exclusively held, unmodified copy of the value and, when a requesting processing unit issues a message indicating that it desires to read the value, and the cache transmits a response indicating that the cache can source the value. The response is transmitted...

Methods for a treatment of cached objects are described. In one embodiment, management of a region of a cache is configured with an eviction policy plug-in. The eviction policy plug-in includes an eviction timing component and a sorting component, with the eviction timing component including code to implement an eviction timing method, and the eviction timing method to trigger eviction of an object from the region of cache. The sorting component includes code to implement a sorting method to ide...

Exemplary embodiments include a multiprocessor system including: a plurality of processors in operable communication with an address manager and an memory controller; and a unified cache in operable communication with the address manager, wherein the unified cache includes: a plurality of cache addresses; a cache data corresponding to each cache address; a data mask corresponding to each cache data; a plurality of cache agents corresponding to each cache address; and a cache state corresponding ...

According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for allowing a variety of transactions to complete locally are implemented by providing remote data caches associated with the various clusters in the system. The remote data caches receive data and state information for memory lines held in remote clusters. If information for responding to a request is available in a rem...