A system that facilitates the storage of data using a write barrier. The system interfaces to a hardware component that stores data, and includes a write barrier component that dynamically employs instructions compatible with the hardware component to ensure data integrity during storage of the data. The write barrier component is independent of at least an operating system and an application and can operate in a least one of a user mode and a kernel mode. The write barrier component includes at...

The present invention relates to a cache flush system and the method for a cache flush performed in cache memory against at least one corresponding prescribed event in a multi-processor system. Embodiments of the present invention can reduce or minimize loads of a processor bus by performing memory read of at most a prescribed size and can increase simultaneousness of cache flush against a corresponding prescribed event by performing a cache flush directly triggered by the prescribed event there...

A method for recovering dirty write cache data after controller power loss or failure from one of two independently battery backed up and mirrored write caches. Two independent controllers jointly operate with a permanent data storage system. Each controller has a write cache that is a mirror of the write cache in the other controller. The primary controller resets a power down flag stored each write cache upon proper shutdown. The primary controller further increments and stores a configuration...

A RAID 0 disk array has an optimizing algorithm for allocating the amount of data stored to each drive in a disk array. The algorithm allocates a proportion of the data for each stripe to the various disk drives based at least in part on the data transfer rate for each drive. The disk array may be constructed such that about half of the disk drives write to the outside tracks of the drives while the remaining disks write to the inside tracks. Using the algorithm, the minimum data transfer rate f...

A cache flush controller, and an associated method, selectably flushes a memory cache of a data processor. The cache flush controller operates at a memory bus level of the data processor and operates to flush a selected line, or lines of the memory cache by writing arbitrary, selected values to the selected line or lines of the memory cache.

A method is provided for a data storage system to move data from a source logical disk (LD) region to a target LD region while the data storage system remains online to a host. The method includes determining if a region move will create excessive load so the data storage system appears offline to the host. If not, the method includes causing writes to the source LD region to be mirrored to the target LD region, causing data in the source LD region to be copied to the target LD region, blocking ...

The cache memory in the present invention is an N-way set-associative cache memory including a control register which indicates one or more ways among N ways, a control unit which activates the way indicated by said control register, and an updating unit which updates contents of said control register. The control unit restricts at least replacement, for a way other than the active way indicated by the control register.

A method and system of enhancing memory performance in a data processing system are provided. The data processing system may include a processor having an on-board first-level cache, a second-level cache coupled to the processor, a system bus coupled to the processor, and a main memory coupled to the system bus. When a memory request is received for a cache line at the first-level cache, a determination is made if the memory request is initiated by a store operation. If the memory request result...

A storage controlling apparatus comprises a store port for holding store data that is transmitted from an arithmetic unit in correspondence with a store request transmitted from an instruction processing device, and is to be written to a cache memory or a memory. The storage controlling apparatus further comprises a data storing unit which receives the store data from the store port, temporarily stores the store data, and comprised between the store port and the cache memory or the memory, and a...

A method for managing use of a fixed memory space of a computer system is provided. The computer system interfaces with controllers for managing operation of devices that operate with the computer system. The method includes determining whether sufficient memory is allocated in the fixed memory space for initializing code for the controllers, and jumping to swappable portion of the fixed memory space. The method also includes executing code in the swappable portion of the fixed memory space. The...