A method and apparatus for increasing the processing speed of processors and increasing the data hit ratio is disclosed herein. The method increases the processing speed by providing a non-L1 instruction caching that uses prefetch to increase the hit ratio. Cache lines in a cache set are buffered, wherein the cache lines have a parameter indicating data selection characteristics associated with each buffered cache line. Then which buffered cache lines to cast out and/or invalidate is determined ...

A self-tuning, low overhead, simple to implement, locally adaptive, novel cache management policy that dynamically and adaptively partitions the cache space amongst sequential and random streams so as to reduce read misses.

A self-tuning, low overhead, simple to implement, locally adaptive, novel cache management policy that dynamically and adaptively partitions the cache space amongst sequential and random streams so as to reduce read misses.

Systems and methods are provided for data caching. An exemplary method for data caching may include establishing a FIFO queue and a LRU queue in a cache memory. The method may further include establishing an auxiliary FIFO queue for addresses of cache lines that have been swapped-out to an external memory. The method may further include determining, if there is a cache miss for the requested data, if there is a hit for requested data in the auxiliary FIFO queue and, if so, swapping-in the reques...

A storage system comprises a volatile cache memory, and a non-volatile memory, which is a type of memory that can continue to memorize data irrespective of whether or not power is supplied. The temporary storage address of data following access commands from the upper level device shall be the volatile cache memory. If power is not supplied from primary power source to the volatile cache memory, power supplied from a battery is used to copy data memorized in volatile cache memory to non-volatile...

A method and means are provided for increasing both the MMBR (minimum misses before replaceable) and MHBR (minimum hits before replaceable) parameters for a virtual 3-way cache, consisting of three unlocked sets, from one to two. Thus, a minimum of two accesses to the sets B, C and D would be required, before a previously accessed set becomes the LRU. In one embodiment, a method is provided for selecting a data set for replacement in a locking cache that includes at least four data sets. Initial...

An information management device includes a setter for setting an address of a file to be monitored, an accessor for accessing the address set by the setter at a prescribed timing, a determiner for determining updating of the file and a controller for controlling image display. The controller displays reduced images of home pages of the files to be monitored in the window of the display with the images being compressed in horizontal direction. The accessor then accesses the previously recorded a...

A method provides for adaptively aging cache segments in a segmented cache in a disk drive. The disk drive receives commands via an intelligent interface from a host. The drive has a magnetic disk. The cache employs a cache control structure including cache parameters, wherein each segment has a scan count of the number of scans of a segment and an access type, and wherein the cache parameters include a maximum number of misses to indicate the maximum number of times a segment will be scanned wi...

A method, apparatus, and computer for identifying selection of a bad victim during victim selection at a cache and recovering from such bad victim selection without causing the system to crash or suspend forward progress of the victim selection process. Among the bad victim selection addressed are recovery from selection of a deleted member and recovery from use of LRU state bits that do not map to a member within the congruence class. When LRU victim selection logic generates an output vector i...

A cache memory device in an N-way (N is an integer of 2 or larger) set associative system includes a way detection unit detecting one way exhibiting a specified strength on the basis of a reference history defined as bits representing a win/loss relation between ways and updated so as to indicate one way exhibiting the specified strength, and an error detection unit detecting a bit error in the reference history if the way detection unit does not detect one way exhibiting the specified strength.