Many conventional lock-free data structures exploit techniques that are possible only because state-of-the-art 64-bit processors are still running 32-bit operating systems and applications. As software catches up to hardware, "64-bit-clean" lock-free data structures, which cannot use such techniques, are needed. We present several 64-bit-clean lock-free implementations: including load-linked/store conditional variables of arbitrary size, a FIFO queue, and a freelist. In addition to being portabl...

Historical access information identifies which resources in a storage area network access portions of shared storage in the storage area network. Based on an analysis of the historical access information, a management report generator application analyzing such information can infer the existence of a cluster of resources that access a common portion of shared storage. When the management report generator identifies that two or more resources access the same storage resources during approximatel...

Methods and apparatus provide for associating memory allocation table (MAT) entries with nodes in a binary tree such that the nodes and the entries are grouped into hierarchical levels, each entry including status information; associating the nodes and the entries with segments of a shared memory of a multi-processor system such that higher level nodes and entries are associated with larger numbers of segments of the shared memory and lower level nodes and entries are associated with smaller num...

There are provided a multisystem network, and a device and method for access to a data storage unit in order to allow processors in a plurality of devices to access the data storage unit. The data storage unit has a data storage area divided in a first area for a first device and a second area for a second device. The first and second devices are connected to the data storage unit via a connection circuit. A first processor in the first device can access directly the data storage unit. The conne...

A storage system includes a storage device, a shared memory, and first and second file server devices that each exclusively manages a respective portion of data stored on the storage device. During operation, the first file server device determines whether the first or second file server device manages data that is subject to the processing of a write command received by the first file server device. When the second file server device manages data that is subject to the processing of the write c...

Described herein are methods and apparatus, including computer program products, that implement a centralized cache storage for runtime systems. A computer program product can include instructions operable to receive a request at a centralized shared cache framework to store an entity; cache the entity in a shared memory in response to the request, where the shared memory is operable to store the entity such that the entity is accessible to runtime systems, and caching the entity in the shared m...

An apparatus and method is disclosed to manage storage coherency in a symmetric multiprocessing environment having a plurality of nodes, each of which contain a multitude of processors, I/O adapters, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. Local controllers on any given node initiate bus operations on behalf of said processors and I/O adapters on that node. Snoop requests are laun...

A shared memory device capable of simplifying wiring to a memory, preventing a decline of performance due to an increase of the area and long wiring, and improving extensibility of scalability of the system is provided: wherein the device has a plurality of memory systems each including a memory macro, a processor, and a memory control unit for controlling an access to a memory macro; wherein the memory control unit of each of the memory systems transfers information between the processor and me...

A computer system having low memory access latency. In one embodiment, the computer system includes a network and one or more processing nodes connected via the network, wherein each processing node includes a plurality of processors and a shared memory connected to each of the processors. The shared memory includes a cache. Each processor includes a scalar processing unit, a vector processing unit and means for operating the scalar processing unit independently of the vector processing unit. Pr...

Embodiments of the instant invention relate to a system for maintaining the integrity of data transfers in shared memory configuration by different processes to a data buffer located in the contiguous memory locations. The accesses by the different processes can be at the same time. One embodiment employs a CISC CPU and a peripheral using a Direct Memory Access (DMA) controller, both of which have an 8-bit data busses. The Memory Interface is provided with a sequencer and registers coupled to a ...