A method for etching a trench in a monocrystal silicon layer. The method includes providing a plasma processing system having a plasma processing chamber. The plasma processing system has a variable plasma generation source and a variable ion energy source with the variable plasma generation source being configured to be controlled independently of the variable ion energy source. The method further includes flowing an etchant source gas that includes O.sub.2, helium, and at least one of SF.sub.6...

A memory test system can screen objects of tests accurately at low cost in quasi-operating conditions by utilizing a personal computer (PC). The system utilizes a PC tester comprising a measurement PC unit that carries a memory module to be used as reference; a signal distribution unit for distributing the signal taken out form the measurement PC unit; a plurality of performance boards (PFBs) mounted with respective objected products to be observed simultaneously by using the signals distributed...

A fuse disposing circuit executes a same test as in a state before a fuse is cut, even in case the fuse is cut. For this, the fuse disposing circuit in accordance with the invention includes a test mode enable confirmation section for informing whether a test mode is enabled; and a fuse set for providing a constant signal by using the output from the test mode enable confirmation section in case of the test mode, regardless of elimination or non-elimination of a fuse.

A memory device test system includes a signal generator providing memory command, address and write data signal to write data in a memory device and then read the data from the memory device. Each item of read data is compared to the corresponding item of write data, and fail data is produced indicative of the results of the comparison. The fail data is applied to a real time repair analyzer, which also receives an address of the read data being read to generate each item of fail data. The addre...

A semiconductor memory device is provided which includes: a plurality of memory cells each formed by latch means; gated clock circuits for writing identical data to all of the memory cells in response to a simultaneous writing signal supplied thereto; inverters for inverting data outputted from the memory cells; and selectors for selectively writing the inverted data to the memory cells.

Crystalline ferroborosilicate compositions are prepared from a silica containing mixture by digesting a reaction mixture comprising a tetraalkylammonium compound, a sodium hydroxide, a boron compound, an oxide of silicon, an iron ion source, an optional chelating agent and water to provide the crystalline ferroborosilicate which is then palladium ion-exchanged. This composition may be used alone or physically mixed with a methanol catalyst. Conversion of synthesis gas, dimethylether, ethylene an...

A 1,3,5-trimethyl-2,4,6-tris(3,5-dialkyl-4-hydroxybenzyl)benzene is prepared in high yield by reacting a 2,6-dialkyl-4-methoxymethylphenol with mesitylene in a hydrocarbon solvent and in the presence of at least about 10 mol %, based on the amount of mesitylene, of a hydrocarbon-soluble acid (e.g., an alkylbenzenesulfonic acid having 12-18 carbons in the alkyl group, a carboxylic acid, or a dialkylsulfosuccinate) as a catalyst or co-catalyst while distilling methanol by-product out of the reacti...

A method for authenticating a digital optical medium to determine if it is original or an unauthorized copy. One or more special bistable data subunits are written onto the original digital optical medium by recording bistable data symbols and other intentional errors into the data subunit such that the data subunit will be on the error-correction limit threshold. A bistable data symbol is a data symbol for which a player will randomly read at least two different values. Depending on which value...

An integrated circuit, a programming mechanism and a method are provided for programming test information upon non-volatile storage devices of the integrated circuit. The test information includes a pass/fail outcome arising from one or more test operations to which the integrated circuit is exposed. In addition to or in lieu of the test outcomes, test results of one or more parametric tests at select test operations can be measured from and programmed back into the integrated circuit. Test limi...

A memory device has a main memory circuit, an auxiliary memory circuit for storing test data, and an interface circuit for transferring test data between the auxiliary memory circuit and external test equipment. Test data are transferred from the external test equipment to the auxiliary memory circuit, then transferred repeatedly to different locations in the main memory circuit. Different test patterns are generated by selectively inverting one bit, or all bits, in the test data as the data are...