Various methods and apparatuses are described for a system that includes some on-chip components, e.g., I-Os, test processors, soft wrappers, etc., an external testing unit that provides Parametric Measurement Unit (PMU) capability, and various tests performed on the I-Os by the on-chip testing logic, the test vector patterns supplied by the external testing unit.

A logic analyzer having internal access to the test buses, clocks and events of a chip is used to debug the chip. The logic analyzer is designed with the capability to share existing memory in the chip during the debug process. Additionally, the configuration of the logic analyzer and observation of the acquired results in the shared memory can be accessed through normal control interfaces of the chip and does not require special test cards. The logic analyzer includes a clocking function, a tri...

The present invention provides a simultaneous switching (SS) test mode. SS test modules supporting an SS test mode are provided. When SS test mode is enabled, SS test mode data is driven on a data bus during an idle bus period. Otherwise, when SS test mode is disabled, no SS test mode data is driven on a data bus during an idle bus period.

A cross-platform test environment automatic setup method and system is proposed, which is designed for use on an information platform that is running on a particular kind of operating system, for the purpose of providing the information platform with a cross-platform test environment automatic setup capability that allows a particular test procedure to be capable of being conducted under the particular kind of operating system on the information platform. The proposed cross-platform test environ...

A test module is provided for testing system modules. All the test circuitry and test connectors reside on the test module. The test module is coupled to the system modules during testing, and is removed from the system after testing. Test connectors and test circuitry on the test module support such test functions as voltage margining, CPU emulation, and JTAG boundary scanning. A JTAG selection function can also be provided for selecting one or more JTAG loops for testing individually or as a s...

A circuit for tracking a number of clock cycles between occurrences of an event of interest. The circuit includes logic for asserting a run signal responsive to a first occurrence of the event of interest, logic for deasserting the run signal responsive to a second occurrence of the event of interest, and logic for incrementing a count value on each clock cycle while the run signal is asserted.

A memory-logics LSI device forms an input/output path for testing. A memory device has a memory input/output unit,which includes an input/output selector with test function. A test clock signal, which is directly supplied in the test mode, is used to selectively take in one of input signals and an output signal to output the signal. The output is monitored on an external pin, while changing the timing of the positive-going edge of the clock signal, or the input signals. Relative measurement is t...

A scannable fast domino output latch is provided. A scannable latch circuit includes a scan logic receiving a scan data input and a scan data clock. The scannable latch circuit includes a transistor stack receiving a data input and receiving a system clock. A first inverter is connected to the transistor stack. The first inverter provides a latch output. A feedback path logic is connected across the first inverter. The feedback path logic is activated responsive to both the system clock and the ...

An integrated circuit is provided with a diagnostic data capture and output system in the form of a diagnostic data capture circuit which captures a data word and a context word from a bus. The bus may be the functional bus connecting functional circuits within the integrated circuit or a dedicated bus linking one or more functional circuits directly to the diagnostic data capture circuit. The diagnostic data captured is buffered within a first-in-first-out buffer and then serialised for output....

A method for testing signals of integrated circuits (ICs). According to the invention, a first IC chip successively drives a number of test patterns one at a time. At the receiving end, a second IC chip latches in the test patterns one by one. Meanwhile, the second IC chip determines whether a currently latched test pattern is correct or not. If it is incorrect and at least an error bit occurs, depending on the type of the test patterns, the second IC chip indicates that there exists ground boun...