A method for determining optimum locations for scan latches using traditional fault-simulation and some additional `bookkeeping.` A logic simulation is run on the IC, with single stuck-at faults injected into the circuit. The entire test set is run and records are kept of which faults are detected at every latch in the system. After the simulation run, the statistics gathered are used to indicate which system latches are the best candidates for conversion to scan latches: A high count of faults ...

Systems and methods for testing a circuit are provided. In one example, a sequential device for use in a scan chain is described. The sequential device may include a scan input, a scan output and a functional data output. The functional data output may be coupled to the scan input and to the scan output. The functional data output may be coupled to the scan output via a delay buffer.

A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that p...

A system and method for isolating defects in scan chains by performing diagnostics fault simulation on chosen faults that are consistent with the nature of a scan chain defect, while keeping information about predictable failures. The effects of defects at specific locations on the scan chain are modeled by compositing the effects of a subset of the faults for each defect. Each composite, which models a specific scan chain defect, is evaluated in terms of how well it predicts the failures measur...

A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106,and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.

A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons...

A method is provided for testing a semiconductor integrated circuit by utilizing a scan path circuit provided to detect the degeneracy fault in the semiconductor integrated circuit, and bringing scan chains to states in which shift resistor operations can be effected for the input of patterns by which a glitch fault and the IR-DROP fault between the scan chains can be detected.

A process initializes the state of an output memory circuit of a scan cell located at the boundary of a logic circuit within an integrated circuit. Data is scanned into an input memory circuit of the cell while maintaining the cell in a mode providing normal operation of the logic circuit. The cell is placed in a test mode that disables normal operation of the logic circuit. The data scanned into the input memory circuit is transferred into the output memory circuit simultaneous with the placing...

The output register of an array and the Multiple Input Signature Register (MISR) logic is implemented with one set of L1/L2 master/slave latches and single additional slave latch. This new combined logic uses less critical area on a chip without a performance impact on the array access time or circuit testing.

A method for eliminating a hold error from a scan chain configured by connecting a plurality of data holding circuits with wiring. The method includes reordering the data holding circuits using the wiring as a delay element to eliminate hold errors from the scan chain. This method eliminates hold errors from the data holding circuits. This keeps the number of buffer circuits inserted between the data holding circuits small and shortens the processing time required for correcting the hold error.