JTAG test equipment arranged to establish an asynchronous data transmission connection with a JTAG-compatible device under test for the transmission of test data between test access ports (TAP) in the test equipment and device under test. The test data is synchronized at reception before the test access ports (TAP). The test equipment includes a computer program for adapting a test data sequence arriving in the format defined by the test access port for transmission on an asynchronous transmissi...

An integrated circuit design block includes combinational and sequential logic defining core logic of the integrated circuit design block, and boundary logic defined at an outer region of the integrated circuit design block. The integrated circuit design block also includes a control test unit that has a scan chain decoder and a boundary scan decoder. The scan chain decoder includes scan chain select circuitry for enabling the scan chain decoder during scan testing of the core logic. The scan ch...

A boundary scan testing system may include a baseboard (102, 202), a computing module (104, 204) coupled to the baseboard, and a boundary scan test module (106, 206, 306, 406) coupled to the computing module, where the boundary scan test module is coupled to execute a boundary scan test (120, 220, 320, 420) on the computing module via a set of boundary scan instructions (114, 214) received remotely over at least one of an IP network (110, 210) and an I.sup.2C bus (211).

Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1, as the scan test stimulus data for another circuit, such as circuit 2. After reset, a scan path captures the output response data from the reset stimulus from all circuits. A tester then shifts the captured data only the length of the first circuit's scan path while loading the first circuit's scan path with new test...

An object of the invention is to provide a boundary scan controller that allows a boundary scan to be executed and also allows a semiconductor apparatus to be manufactured in such a manner that the same type of semiconductor circuit chips are stacked. When identification data stored in memory means (85) is compared with fixed data held in fixed-data holding means (87) by comparison means (88) and the identification data is coincident with the fixed data, a data derivation section (89) outputs th...

Peripheral input and output buffer circuitry is tested using scan path circuitry selectively connecting external signals TSA, TSB, and TSC to the buffer circuitry. This is in addition to testing the internal circuitry of the integrated circuit with the scan path circuitry. An external signal, TSC, provides a load to the output of the buffer circuitry. An external signal, TSA, receives a response from input buffer circuitry and supplies a stimulus signal to output buffer circuitry. An external si...

An integrated circuit provides for a connection port having a serial data input pin and a serial data output pin, on-chip functional circuitry and test logic, and a test access port controller connected to effect communication of serial data across the chip boundary via said input and output pins. The test access port controller is connectable to the test logic in a first mode of operation to effect communication of serial test data under control of an incoming clock signal and is operable in a ...

The present disclosure describes a system and method for testing component IC chips. The system includes a management controller that has an embedded JTAG test routine operable to test one or more component IC chips associated with the management controller. The system further includes a memory associated with the management controller and the management controller is further operable to save a JTAG test routine result within the memory. More specifically, the management controller is operable t...

Serial scanning circuitry is connectable to test access port controller for transferring serial data to and from functional circuitry. The test access port controller includes a first state machine having plural states controlling the transfer of serial data. Additional control circuitry includes a second state machine connected to the serial scanning circuitry and connected to the test access port controller. The additional control circuitry, when connected to the test access port controller, e...

An electronic integrated circuit includes a signal path connected between the functional logic and an external input terminal, which signal path includes a memory circuit. The memory circuit is coupled to the input terminal and is selectively operable to detect and resolve voltage contention at the input terminal, and is also selectively operable to isolate itself from voltages at the input terminal. The memory circuit has two data inputs, one from the input terminal and the other from a serial ...