Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches ...

A BIST circuit for use with a read channel device is disclosed that utilizes internally generated clock and control signals to control a test sequence. A linear feedback shift register is used as the signature analysis register. The test signature accumulation process is controlled by clock and control signals internal to the read charnel device that are associated with the normal operation of the read channel device.

System and method for automatic fault-testing of a logic block and the interfaces of macros with logic gates inside a chip, using an at-speed logic-BIST internal to the chip. Following an initialization of internal storage elements, a set of test signals are generated and processed by the logic block. The output of the logic block is accumulated into a signature and compared to a reference signature to detect faults. Testing can be performed on an ATE (Automatic Test Equipment) using a simple te...

An apparatus and method for automatically calibrating a duty cycle circuit for maximum performance. A chip level built-in circuit automatically calibrates the duty cycle correction (DCC) circuit setting for each chip. The chip level built-in circuit includes a clock generation macro unit, a simple duty cycle correction (DCC) circuit, an array slice and built-in self test unit, and a DCC circuit controller. A built-in self test provides results, i.e. pass or fail, of an array to the DCC circuit c...

An eye width characterization mechanism determines a pass setting of a sampling phase positioned within an eye width of received data. The sampling phase is incremented in a first direction from the pass setting until the sampling phase is outside the eye width of the received data. The sampling phase is then incremented in an opposite direction of the first direction starting again from the pass setting until the sampling phase is outside the eye width of the received data. The number of the sa...

An apparatus and method for automatically calibrating a duty cycle circuit for maximum performance. A chip level built-in circuit automatically calibrates the duty cycle correction (DCC) circuit setting for each chip. The chip level built-in circuit includes a clock generation macro unit, a simple duty cycle correction (DCC) circuit, an array slice and built-in self test unit, and a DCC circuit controller. A built-in self-test provides results, i.e. pass or fail, of an array to the DCC circuit c...

A process for synthesizing light paraffinic hydrocarbons, preferably C.sub.1 -C.sub.3 in carbon number, from CO and steam is described utilizing novel molybdenum oxycarbonitride catalyst.

A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error sy...

An integrated circuit arrangement including at least one circuit part which is designed to run through a functional self test and to output test results of the functional self test, and a testing unit, which is coupled to an input and an output and which is coupled to the at least one circuit part via testing lines. The testing unit is designed to start the functional self test when a starting signal for the functional self test is applied to the input, to evaluate test results that are present ...

In an embodiment, a phase interpolator (PI) circuit is in an integrated circuit with a test latch, and the test latch is enabled by a test clock signal to under-sample the PI output clock signal from the signal source. In a method of operation, a PI output clock signal is generated in an integrated circuit, and the PI output clock signal is under-sampled in a test latch in the integrated circuit triggered by a test clock signal. Output data from the test latch is transmitted to a test device tha...