The on-chip data transmission controller comprises a data comparison unit for comparing current data with previous data and issuing an inversion flag if the number of data bits phase-transited is larger than a preset number, a first data inversion unit for inverting a phase of the current data when the inversion flag is activated and providing inverted data onto a data bus, and a second data inversion unit for inverting a phase of the data transmitted via the data bus when the inversion flag is ...

The invention relates to a method for testing a memory device with the memory device being able to be operated in a normal operating mode and a test mode and encompassing an output driver, input driver, and data pads. The method includes the steps of communicating test input data to be used for a test to the memory device, performing a test using the test input data in order to obtain test output data, the test data read out being passed via an output driver, at least one data pad, and an input ...

A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register (34), test port (38) and output control circuits (42, 46) controlled by an event qualifying module (EQM) (32). In response to a matching condition the EQM (32) may perform a variety of tests on incoming data while the integrated circuits (10, 12) continue to operate at speed. A plurality of digital bus monitors (20, 22) may be cascaded ...

In evaluating the location of a failure in a logic circuit including gates defined in a hierarchical manner, the present invention discloses a system capable of evaluating the location of a failure by referring to the circuitry of a gate described by a basic gate without creating any special databases that are dedicated to evaluating the location of a failure. In this system, expected value setting device obtains an expected value of a target gate inside the logic circuit by an IF-THEN operation...

The quality of data stored in a memory system is assessed by different methods, and the memory system is operated according to the assessed quality. The data quality can be assessed during read operations. Subsequent use of an Error Correction Code can utilize the quality indications to detect and reconstruct the data with improved effectiveness. Alternatively, a statistics of data quality can be constructed and digital data values can be associated in a modified manner to prevent data corruptio...

A method and apparatus that uses device defects as an identifier. Data is written to memory of an integrated circuit. Defects are identified based upon the writing of the data. An identifier for the IC is then derived using the identification of the defects.

A programmable source/measurement module for automatic test equipment is disclosed. A high resolution low frequency source, high resolution low frequency measurement capability, low resolution high frequency source, and a low resolution high frequency measurement capability are provided in a single module. The module comprises an input/output switch matrix selectively coupled to a low frequency filter block and a high frequency filter block. Each filter block may be used for either source or mea...

A test apparatus including a means for sending a first test pattern to a device under test (DUT), where the first test pattern is a part of a planned sequence of tests, and further including a means for evaluating the test results received from the DUT, and a method of testing are described. The test results may include anomalous data indicative of a defect in the DUT. If so, a second test pattern that is not part of the planned sequence of tests is selected. The second test pattern is selected ...

A method of locating faults occurred in an LSI (Large Scale Integrated Circuit) is disclosed. Block-by-block logic information each varying in accordance with a test vector are output by dump processing using logic simulation on the basis of circuit connection information. The block-by-block logic information varying in accordance with the test vector are combined with Iddq information showing whether or not an Iddq error has occurred test vector by test vector. These information are used to exe...

A circuit generally including a control function and a checksum function is disclosed. The control function may be configured to assert (i) a start signal in response to a signal having a predetermined sequence of values matching an entry value and (ii) a stop signal in response to the signal matching an exit value. The checksum function may be configured to (i) generate a checksum value for the signal between assertions of the start signal and the stop signal and (ii) generate a result signal i...