A signal generator for generating an output signal corresponding to pattern data includes (i) a plurality of timing generators that generate a plurality of periodic signals each having a different phase with respect to a reference clock, (ii) a shift register section including a plurality of flip-flops in a cascade arrangement through which each piece of pattern data is propagated sequentially in response to a first periodic signal output from a first timing generator, (iii) a plurality of regis...

A memory includes a data generator to generate a data pattern, a transmitter in communication with the data generator, the transmitter to transmit the data pattern as a test data pattern, receiver to receive the test data pattern from the transmitter, and a comparator coupled with the receiver, the comparator to compare the data pattern with the test data pattern from the receiver and to verify proper operation of a memory channel. A method includes providing a seed value to a transmit and a rec...

Described herein are methods and systems for distributed execution of circuit testing algorithms, or portions thereof. Distributed processing can result in faster processing. Algorithms or portions of algorithms that are independent from each other can be executed in a non-sequential manner (e.g., parallel) over a network of plurality of processors. The network includes a controlling processor that can allocate tasks to other processors and conduct the execution of some tasks on its own. Depende...

A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults ("TDF")) wherein when either a slow-to-rise (STR) or a slow-to-fall (STF) transition fault is detected, that specific fault is removed from a fault universe as well as its companion TDF, wherein the companion fault is a fault on the same node as the detected fault but has the opposite transition. In other words, if a slow-to-rise (STR) transition fault is detected, the slow-to-r...

Constraining sequential data expressing sequential data which a sequential pattern to be extracted must include is specified in advance. Sequential pattern candidates with sequence length 1 are initially determined from among a plurality of input sequential data. Next, a set of sequential pattern candidates is generated by determining a plurality of new sequential pattern candidates by elongating the sequence length of the sequential pattern candidates. In this sequential pattern candidate set, ...

A pattern generator includes a main memory for storing a plurality of sequence data blocks for generating a test pattern, a first sequence cache memory for sequentially storing the sequence data blocks, a second sequence cache memory, a data development section for sequentially executing the sequence data blocks stored in the first cache memory and generating a test pattern and a read-ahead means, when the data development section detects a read-ahead instruction on reading ahead the other seque...

A test pattern generating apparatus includes an extractor configured to extract a plurality of layout parameters (elements) of a circuit under test based on gate net information and layout information of the circuit, and to link the layout parameters (elements) with corresponding fault models respectively. A weight calculator is configured to calculate a weight for each fault model linked with the layout parameters (elements) for both a plurality of undetected faults of the fault model and a plu...

The present invention is directed to a system and method for quality improvement by identifying test patterns for DFT logic faults and functional logic faults. The identified test patterns may be selectively utilized for pruning of patterns or DPM estimation. Functional faults and DFT faults may be identified from detected TDF faults. The functional faults are faults on a logic which was present in a pre-test insertion net list. Remaining faults are the DFT faults. A set of test patterns for DFT...

A method and an apparatus provides for calibrating a test system for an integrated semiconductor circuit, a pattern generator of the test system generating a test signal in the form of a pattern of successive rising and falling edges, which is composed of superposed sub-patterns formed via different internal paths of the pattern generator. The pattern generator provides an information signal for a measuring device of the test system, which identifies the edges of at least one sub-pattern of the ...

A first device delivers a clock offset message to a second device. The second device offsets its data transmission according to the clock offset message. A test pattern is transmitted from the second device to the first device. The first device then checks the received test pattern to determine whether the transmission was successful. The first device can then deliver an additional clock offset message to the second device to instruct the second device to offset its data transmission by a differ...