A REPEAT instruction for repeated execution of an associated instruction (INST.sub.R). Once a program counter stores the address for the instruction to be repeated, it remains unchanged until the associated instruction (INST.sub.R) has been executed the number of times indicated by a COUNT value in a preloaded register, or alternatively, by the REPEAT instruction itself. In this manner, the present invention reduces the number of instruction fetches required to repeatedly execute the associated ...

A system for the encryption and decryption of data employing dual ported RAM for key storage to accelerate data processing operations. The on-chip key storage includes a dual-ported memory device which allows keys to be loaded into memory simultaneous with keys being read out of memory. Thus, an encryption or decryption algorithm can proceed while keys are being loaded into memory.

A power conservation system which provides for fast and efficient transitions between fast and slow processor clocking speeds. The slow processor clocking speed minimizes power consumption during periods of processor inactivity (idle states) or low priority execution. The fast processor clocking speeds are utilized during periods of processor activity (active states) or high priority execution. Used in conjunction with a context-sensitive processor, the power conservation system is able to monit...

A system for the encryption and decryption of data employing dual ported RAM to accelerate data processing operations during the computation of the encryption and decryption algorithm. The system includes logic to track data changes in the dual ported memory for fast table initialization; a means to accelerate operations by performing read/write operations in different iterations of the algorithm to separate ports on the dual ported RAM in the same clock cycle; and a means to resolve data manipu...

A queuing system utilizing dual first-in, first-out (FIFO) memories is provided. The present queuing system is configured to use a first FIFO memory to receive and transfer a plurality of frames to a second FIFO memory wherein the frames include encrypted frame contents. The first FIFO memory is configured to transfer an interrupt to an associated processor in response to completion of the receipt of a valid frame. Next, the processor is configured to reinitialize the first FIFO memory for recei...

A system for the encryption and decryption of data employing cycle stealing to accelerate data processing operations. The cycle stealing is employed by using level sensitive latches in a microcode controller system for storing addresses and code words. The microcode controller system controls the data path hardware for executing the encryption/decryption operations.

Techniques for implementing caches for context switching applications are provided. A context identifier is stored in the cache to indicate the context to which data in the cache is associated. Additionally, the context can have different priorities so that storage space in the cache can be more efficiently allocated to the contexts based on their priorities.

A priority-based arbiter for arbitrating access to a shared resource by at least two competing devices. The priority-based arbiter intercepts access request signals generated by at least one of the competing devices and generates a respective modified bus request signal. The respective modified bus request signal may be delayed for a predetermined period of time associated with the state (e.g., idle, low priority context, and high priority context) of at least one of the competing devices.

A system for the encryption and decryption of data employing dual ported RAM for key storage to accelerate data processing operations. The on-chip key storage includes a dual-ported memory device which allows keys to be loaded into memory simultaneous with keys being read out of memory. Thus, an encryption or decryption algorithm can proceed while keys are being loaded into memory.

Techniques for implementing caches for context switching applications are provided. A context identifier is stored in the cache to indicate the context to which data in the cache is associated. Additionally, the context can have different priorities so that storage space in the cache can be more efficiently allocated to the contexts based on their priorities.