A process is described for forming an opening for a contact member through a deposited oxide layer and thermally grown oxide layer. Where the deposited oxide layer is rich in phosphorus, a wet etchant is used to etch through the deposited oxide layer. This results in a tapered opening through the deposited oxide layer. Then a plasma etchant is used to form an opening through the thermally grown oxide in alignment with an opening through a photoresist layer.

An integrated circuit is fabricated with a layer of polysilicon located on top of shallow trench regions. The polysilicon is patterned so that the trench features are not exposed during an etching operation performed on the polysilicon layer. The process of fabricating transistor gate electrodes, therefore, is improved by reducing etch byproducts contributed by the shallow trench region features.

An integrated circuit is fabricated with a layer of polysilicon located on top of shallow trench regions. The polysilicon is patterned so that the trench features are not exposed during an etching operation performed on the polysilicon layer. The process of fabricating transistor gate electrodes, therefore, is improved by reducing etch byproducts contributed by the shallow trench region features.

A structure suitable for connecting an integrated circuit to a supporting substrate wherein the structure has thermal expansion characteristics well-matched to the integrated circuit is an interposer. The integrated circuit and the interposer are comprised of bodies that have substantially similar coefficients of thermal expansion. The interposer has a first surface adapted to electrically and mechanically couple to the integrated circuit. The interposer has a second surface adapted to electrica...

A novel passivation structure and its method of fabrication. According to the present invention a first dielectric layer is formed upon a conductive layer formed over a substrate. The first dielectric layer and the conductive layer are then patterned into a first dielectric capped interconnect and a dielectric capped bond pad. Next, a second dielectric layer is formed over and between the dielectric capped interconnect and the dielectric capped bond pad. The top portion of the second dielectric ...

A novel passivation structure and its method of fabrication. According to the present invention a first dielectric layer is formed upon a conductive layer formed over a substrate. The first dielectric layer and the conductive layer are then patterned into a first dielectric capped interconnect and a dielectric capped bond pad. Next, a second dielectric layer is formed over and between the dielectric capped interconnect and the dielectric capped bond pad. The top portion of the second dielectric ...

Method and apparatus for fabricating contacts to substrate regions through a low k, low density dielectric. A cap is formed over gates and side spacers are formed along the edges of the gates so as to surround the gates in a relatively dense (e.g., silicon dioxide) insulative material. A low k or low density layer of a polymer or silica aerogel or xerogel material is formed in contact with the substrate covering the gate structures including the spacers. An unlanded contact opening is etched thr...

A structure suitable for connecting an integrated circuit to a supporting substrate wherein the structure has thermal expansion characteristics well-matched to the integrated circuit is an interposer. The integrated circuit and the interposer are comprised of bodies that have substantially similar coefficients of thermal expansion. The interposer has a first surface adapted to electrically and mechanically couple to the integrated circuit. The interposer has a second surface adapted to electrica...

The deposition of oxide over a semiconductor substrate to fill trenches provides for simpler isolation processing for semiconductor circuit fabrication. Both shallow and deep trenches are etched in a semiconductor substrate for the formation of both device isolation structures and well isolation structures. Oxide is then deposited using chemical vapor deposition over the substrate, filling both the shallow and deep trenches. The resulting oxide layer over the substrate is then planarized, thus f...

The present invention is a silicon on insulator (SOI) transistor and its method of fabrication. According to the present invention, an opening is formed in the insulating layer formed on a single crystalline silicon substrate. An amorphous or polycrystalline silicon or silicon alloy is then formed in the opening on the single crystalline silicon substrate and on the insulating layer. The amorphous or polycrystalline silicon or silicon alloy in the opening and at least a portion of the amorphous ...