A video line connection apparatus for adaptively connecting external input/output lines, the apparatus capable of flexibly selecting an output by responding to the external line which is connected to an input jack. The apparatus includes: a plurality of composite video input jacks; a plurality of Y/C separated video input jacks; at least one composite video output jack; at least one Y/C separated video output jack; a first multiplexer; a second multiplexer; a third multiplexer; a luminance/chrom...

A five-forward speed automatic transmission, includes: a torque convertor connected to an output shaft of an engine for changing and transmitting engine torque; an input shaft connected to an output member of the torque convertor; first, second and third planetary gearsets disposed between the input and output shafts so as to shift power transmitted to the input shaft in five-forward speeds and one reverse speed; a first clutch selectively connecting a sun gear of the second planetary gearset to...

A magnetic random access memory (MRAM) includes a first memory array having a plurality of first memory cells, wherein each one of the plurality of first memory cells is arranged at an intersection of at least one of a plurality of wordlines, at least one of a plurality of bitlines, and at least one of a plurality of digit lines, a second memory array having a plurality of second memory cells, wherein each one of the plurality of second memory cells is arranged at an intersection of at least one...

An automatic variable transmnission, and a hydraulic pressure control system for the same, have a structure which can be installed in both rear and front wheel drive vehicles. The transmission includes: a torque converter which is connected to an output shaft of an engine and which converts and transfers torque from the engine; an input shaft connected to the output shaft of the torque converter; first and second planetary gearsets which are located between the input shaft and an output shaft; a...

A method for interpolating pixel data of an omitted line by use of pixel data from an interlaced scan and an apparatus therefor are described. The pixel interpolation method and apparatus efficiently interpolate edges having various slopes according to a degree of correlation. When an edge has a gentle slope due to extensive correlation, interpolation is performed using a wide-vector. When an error occurs due to high-frequency components such as when bidirectional edges are found, simple vertica...

A nonvolatile semiconductor memory device comprising a main memory cell array and a spare memory cell array, capable of freely accessing data in the spare memory cell array irrespective of the physical addresses of the spare memory cell array, and a method thereof are disclosed. The logical addresses of the spare memory cell array are assigned prior to the logical addresses of the main memory cell array in response to a first control signal, and data stored in the spare memory cell array is read...

A multi-level semiconductor memory device preferably includes a plurality of wordlines connected to memory cells configured to store multi-level data. A first circuit supplies a temperature-responsive voltage to a selected wordline in order to read a state of a selected memory cell. A second circuit supplies a predetermined voltage to non-selected wordlines. The first circuit preferably includes a semiconductor element that varies its resistance in accordance with temperature. Reliable program-v...

A circuit and method for programming phase-change memory devices, such as chalcogenide memory (PRAM), are described. The invention is directed to an approach to programming PRAM elements from a reset state to a set state or from a set state to the set state. The invention provides a novel and nonobvious PRAM device and method in which a set pulse duration time is controlled by monitoring the state of the memory element during programming such as by comparing the voltage of a bit line with a refe...

Programming phase-change memory devices and driver circuits for programming phase-change memory devices are provided that control an amount of current supplied to a phase-change material of the phase-change memory device based on a measure of resistance of the phase-change material during programming of the phase-change memory device. Such control may be based on detected voltage or current. The amount of current supplied to the phase-change material may be increased until the measured voltage l...

A nonvolatile memory device includes a bit line, a pair of data lines and a plurality of scalable two transistor memory (STTM) cells. The memory cells are arranged between a pair of datalines so as to share the bit line. The memory device further includes a data line selection circuit and a sense amplification circuit. The data line selection circuit selects one of a pair of data lines, and the sense amplification circuit senses and amplifies a voltage difference between the bit line and the sel...