An output stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips, is comprised of multiple input registers which hold input addresses and input data words; and a multiplexer circuit, having a plurality of parallel data inputs which concurrently receive the input addresses and the input data words, having control inputs for receiving a sequence of control signals, and which generates serial bit streams by selectively passing bits from the input addre...

An intermediate stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips, is comprised of a plurality of input address registers which hold respective input addresses; and a memory address generator, coupled to the input address registers, which generates a series of memory addresses by selecting bits from the input addresses. A memory is coupled to the memory address generator, which sequentially receives each memory address in the series; and in res...

An initial stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips, is comprised of multiple sets of input registers which store respective addresses; and an address modifying circuit that is coupled to the input registers, which receives commands, and in response, selects one register in one set and generates a modified address by performing arithmetic operations on the address in the selected register. Also, the initial stage includes a boundary ch...

A multi-stage algorithmic pattern generator, which generates bit streams for testing IC chips, is comprised of an initial stage, an intermediate stage, and an output stage which are coupled together as a three stage pipeline. The initial stage sequentially generates multiple sets of virtual addresses for a virtual memory in response to a series of instructions from an external source. The intermediate stage sequentially stores each set of virtual addresses from the initial stage and translates t...

A system for testing integrated circuit chips is comprised of a selectable number of pattern generators, each of which is coupled via a separate bus to a selectable number of chip driver circuits. Each pattern generator also is coupled to a respective memory, which stores different bit streams that are readable one word at a time. In operation, each pattern generator selectively reads the bit streams, word by word, from its respective memory; and its sends the words that are read to all of the c...

A system for testing IC chips selectively with stored or internally generated bit streams is comprised of a memory which stores instructions of a first class that expressly recite a first bit stream, and stores instructions of a second class that specify operations which generate a second bit stream. A first pattern generator is coupled to the memory, which sequentially reads the instructions of the first and second classes. The first pattern generator includes a time-shared control circuit whic...

A system for testing integrated circuit chips is comprised of a pattern generator that is coupled to a memory which stores variable length instructions that specify sets of bit streams for testing the chips. Each variable length instruction includes a code which indicates the number of bit streams in the set. Each bit stream in the set consists of a selectable number of bits which start on a word boundary and vary in increments of one bit. If the code indicates that the number of bit streams in ...

A system for testing integrated circuit chips includes a signal generator which generates a clock signal; and a sequential control circuit having a first input which receives the clock signal, a second input for receiving commands, and multiple outputs. A command source sends programmable sequences of the commands to the second input of the control circuit; and in response, the control circuit passes the clock signal from the first input to only certain outputs which the commands select. All of ...