The present invention provides for supporting an on chip-timer facility and, more particularly, to the generation of a constant time incremental increase while changing core mesh-clock frequency. A latch is coupled to the output of a first free-running clock. An inverter is coupled to the output of the first latch. At least one other secondary latch is coupled to the output of the first latch. An edge detector is coupled to the output of the secondary latch. An incrementer or decrementer is coup...

A method and apparatus for efficiently storing an effective address (EA) in an effective to real address translation (ERAT) table supporting multiple page sizes by adding PSI fields, based on the number of unique page sizes supported, to each ERAT entry and using one ERAT entry to store an EA for a memory page, regardless of page size, by setting the PSI fields to indicate the page size.

A write-through cache scheme is created. A store data command is sent to a cache line of a cache array from a processing unit. It is then determined whether the address of the store data is valid, wherein the original data from the store's address has been previously loaded into the cache. A write-through command is sent to a system bus as a function of whether the address of the store data is valid. The bus controller is employed to sense the write-through command. If the write-through command ...

A method, an apparatus and a computer program product are provided for the managing of SIMD instructions and GP instructions within an instruction pipeline of a processor. The SIMD instructions and the GP instructions share the same "front-end" pipelines within an Instruction Unit. Within the shared pipelines the Instruction Unit checks the GP instructions for dependencies and resolves these dependencies. At the dispatch point within the pipelines the Instruction Unit sends valid GP instructions...

A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution pipeline may include logic for allowing instructions to flow from the backup pipeline to the regular pipeline following the flushing of the instructions younger than the exception detec...

The present invention provides for a cache-accessing system employing a binary tree with decision nodes. A cache comprising a plurality of sets is provided. A locking or streaming replacement strategy is employed for individual sets of the cache. A replacement management table is also provided. The replacement management table is employable for managing a replacement policy of information associated with the plurality of sets. A pseudo least recently used function is employed to determine the le...

The present invention provides a method, a computer program product, and an apparatus for blocking a thread at dispatch in a multi-thread processor for fine-grained control of thread performance. Multiple threads share a pipeline within a processor. Therefore, a long latency condition for an instruction on one thread can stall all of the threads that share the pipeline. A dispatch-block signaling instruction blocks the thread containing the long latency condition at dispatch. The length of the b...

A computer implemented method and system for managing replacement of sets in a locked cache. A cache access by a program is performed, and a side of a binary tree pointed to by a base leaf is identified. A determination is made as to whether a number of accesses to the identified side of the binary tree equals a number of sets associated with the program on the identified side. The base leaf is changed to point to an opposite side of the binary tree if the number of accesses to the identified si...

Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is ...

A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the down...