A computer includes a memory for storing the machine instructions therein and an arithmetic logic unit for carrying out logical and arithmetic operations. An instruction processing unit is provided for receiving and decoding machine instructions which are received from the memory. The instruction processing unit produces an entry address for the first microinstruction which corresponds to the machine instruction which was decoded by the instruction processing unit. A dispatch control store is co...

An embodiment of the invention provides a method for migrating data from one location to another comprising establishing a new memory location under control of a specific memory accessing device. The new memory location being where data, which is being migrated from a first memory location, is to be resident, the specific accessing device taking control of a certain portion of data resident at the first memory location, the control preventing the certain data from being accessed by any device ot...

An embodiment of the invention provides a method for migrating data from one location to another comprising establishing a new memory location under control of a specific memory accessing device. The new memory location being where data, which is being migrated from a first memory location, is to be resident, the specific accessing device taking control of a certain portion of data resident at the first memory location, the control preventing the certain data from being accessed by any device ot...

A controller arrangement and method for effectuating data transfer between a first clock domain and a second clock domain. In one embodiment, inversion circuitry inverts a first clock signal associated with the first clock domain into an inverted first clock signal that is used in effectuating a SYNC pulse during coincident edges of the inverted first clock signal and a second clock signal associated with the second clock domain. Clock synchronizer controller circuitry operates responsive to sam...

A match circuit connected to a bus carrying data is described. In one embodiment, the match circuit includes logic for activating a decoded_match signal, the logic for activating a decoded match signal comprising logic for decoding a sum field comprising a selected portion of the data into a decoded_sum signal, wherein an active bit of the decoded_sum field corresponds to a value of the sum field; and logic for comparing the decoded_sum signal with a mask signal and outputting a binary bit compr...

A system and method for single hop, processor-to-processor communication in a multiprocessing system over a plurality of crossbars are disclosed. Briefly described, one embodiment is a multiprocessing system comprising a plurality of processors having a plurality of high-bandwidth point-to-point links; a plurality of processor clusters, each processor cluster having a predefined number of the processors residing therein; and a plurality of crossbars, one of the crossbars coupling each of the pro...

A computer (20) is configured for optimizing the processing rate of instructions and the throughput of data. The computer (20) includes a main memory (99), a memory control unit (22), a physical cache unit (100), and a central processor (156). A instruction processing unit (126) is included within the central processor (156). The function of the instruction processing unit (126) is to decode instructions and produce instruction execution commands or directing the execution of the instructions wi...

A computer system comprises a plurality of independent processors which can either execute a separate process for each processor, or execute parallel process operations across multiple processors for one process. The computer system includes a set of communication registers divided into a group of frames and a set of semaphores which correspond respectively to the registers. Typical processes have both serial and parallel code segments. During serial execution, a process is executed by a single ...

A computer system having a plurality of independent processors which can either execute a separate process for each processor, or execute parallel process operations across multiple processors for one process. The computer system includes a set of communication registers divided into a group of frames and a set of semaphores which correspond respectively to the registers. Typical processes have both serial and parallel code segments. During serial execution, a process is executed by a single pro...

A system and method for facilitating communications between a plurality of devices that communicate using different cache-line sizes are disclosed. Briefly described, in architecture, one exemplary embodiment of a compatible cache-line communication system employs a plurality of first ports, each first port configured to receive communications from a first type of device that uses a first cache-line size; and a plurality of second ports, each second port configured to receive communications from...