A method for fabricating a dual damascene structure. A cap layer and a dielectric layer are formed in sequence over a substrate having a first conductive layer. A trench and a via hole are formed in the dielectric layer. The via hole is aligned under the trench. A barrier spacer is formed on sidewalls of the trench and the via hole. The cap layer exposed by the via hole is removed. A conformal adhesion layer is formed over the substrate. A second conductive layer is formed over the substrate and...

A dual damascene process for producing interconnects. The dual damascene process includes forming an etching stop layer over a substrate having a conductive layer therein, and forming an inter-layer dielectric layer over the etching stop layer. A mask layer is formed over the dielectric layer. The mask layer and the inter-layer dielectric layer are patterned to form an opening that expose a portion of the etching stop layer. The opening is formed above the conductive layer. Photoresist material ...

A degradation-free, low-permittivity dielectrics patterning process for damascene starts with provision of a substrate, wherein the substrate has a dielectric layer and a via plug formed on it. Then, a inter-metal dielectric layer and an insulating layer are formed in sequence on the dielectric layer. A hard mask layer is next formed on the insulating layer, and is subsequently patterned. An etching process is performed on the insulating layer and the inter metal dielectric layer by using the pa...

An improved method for forming a dual damascene structure is described. A via opening of the dual damascene structure is formed in a dielectric layer. A non-conformal cap layer is then formed on the substrate before the step of defining the photoresist layer. The non-conformal cap layer only covers the top region of the trench but does not fill the trench. A patterned photoresist layer is then formed on the substrate followed by an etching procedure so as to form a trench. The photoresist layer ...

The present invention provides a method of forming a bonding pad on a semiconductor chip such that peeling of bonding pads during interconnection in the packaging process is avoided. The bonding pad is used to electrically connect an integrated circuit in the semiconductor chip with an external circuit. The method comprises forming a first dielectric layer at a predetermined area on the surface of the semiconductor chip, forming a second dielectric layer on the surface of the semiconductor chip ...

The present invention provides a bonding pad on a semiconductor chip such that peeling of bonding pads during interconnection in the packaging process is avoided. The bonding pad is used to electrically connect an integrated circuit in the semiconductor chip with an external circuit. The semiconductor chip comprises a first dielectric layer positioned in a predetermined area on the surface of the semiconductor chip, a second dielectric layer positioned on the surface of the semiconductor chip ou...

The present invention provides a semiconductor chip. The semiconductor chip comprising an integrated circuit (IC) positioned within the semiconductor chip, and a bonding pad positioned on the surface of the semiconductor chip and electrically connected with the IC. The method comprises using a probe to contact a predetermined testing area on the surface of the bonding pad to electrically test the IC, and forming a passivation layer on the surface of the semiconductor chip to passivate the surfac...

The present invention provides a method of testing and packaging a semiconductor chip. The semiconductor chip includes an integrated circuit (IC) positioned within the semiconductor chip, and a bonding pad positioned on the surface of the semiconductor chip and electrically connected with the IC. The method includes using a probe to contact a predetermined testing area on the surface of the bonding pad to electrically test the IC, and forming a passivation layer on the surface of the semiconduct...

A dielectric pattern. On a substrate having a metal wiring layer formed thereon, a first dielectric layer and a first masking layer are formed. A cap insulation layer is formed on the masking layer. The first dielectric layer, the first masking layer and the cap insulation layer are penetrated through by a first opening. A second dielectric layer and a second masking layer are formed on the cap insulation layer. The second dielectric layer and the second masking layer are penetrated through by a...

A method of fabricating an unlanded metal via of multi-level interconnection. The method is characterized by utilizing damascene scheme to form a metal wiring layer so that the processes are simplified. Moreover, by this method of the invention, a problem of difficulty in filling dielectric material between the metal wiring lines can be avoided and the metal layer does not have to be etched prior to filling the dielectric material. Further more, an etching stop layer is formed over the first int...