A method and apparatus that couple a change input scan chain test pattern with an initialization scan chain test pattern such that a resultant scan chain test pattern is produced, and apply the resultant scan chain test pattern to at least one combinational logic path. In one embodiment, the coupling is achieved by interleaving the change input scan chain test pattern with the initialization scan chain test pattern. In another embodiment, the coupling is achieved by creating a constructed test p...

A method and apparatus that couple a change input scan chain test pattern with an initialization scan chain test pattern such that a resultant scan chain test pattern is produced, and apply the resultant scan chain test pattern to at least one combinational logic path. In one embodiment, the coupling is achieved by interleaving the change input scan chain test pattern with the initialization scan chain test pattern. In another embodiment, the coupling is achieved by creating a constructed test p...

An apparatus comprising a first bus segment, a second bus segment and a switch. The first bus segment may be configured to transfer data in either a first direction or a second direction. The second bus segment may be configured to transfer data in either the first direction or the second direction. The switch may be connected between the first bus segment and the second bus segment. The switch may be configured to transfer data in both the first direction and the second direction simultaneously...

A digital system in a first clock domain synchronously initializes a logic circuit having a memory characteristic. The digital system includes first and second logic circuits. The first circuit includes an asynchronous port for receiving a reset signal from a second clock domain, a port for receiving a first clock signal for the first clock domain, and an output port for providing an initialization signal. The first circuit sets the initialization signal at a first logic value in response to the...

A sigma delta signal treating apparatus includes: (a) a low pass filtered signal path including at least one low pass filter; and (b) a quantization noise filtered signal path coupled with the low pass filtered signal path; the quantization noise filtered signal path including at least one high pass filter and at least one feedback notch filter.

A method and circuit for allowing direct access logic testing in integrated circuits. In one embodiment, an interface between integrated circuit core logic and integrated circuit user-defined logic is exposed, and the integrated circuit core logic and the integrated circuit user-defined logic is tested via the exposed interface. In another embodiment, an integrated circuit has logic selection circuitry connected with core logic and user-defined logic. The logic selection circuitry is used to sel...

Various systems and methods for analog to digital conversion are disclosed. For example, some embodiments of the present invention provide analog to digital conversion systems. The analog to digital conversion systems include a first integrator and a second integrator, and a first summation element and a second summation element. An output of the first summation element is electrically coupled to the first integrator, and an output of the first integrator is electrically coupled to the second in...

An apparatus comprising a memory, a plurality of modules, an address translation unit and a controller. The memory may be arranged as a plurality of memory banks. Each of the plurality of modules may be configured to generate one or more addresses for accessing a particular one of the plurality of memory banks. The address translation unit may be configured to modify the one or more addresses in response to a control signal. The controller may be configured to generate the control signal in resp...