This specification describes an associative memory decoder for a memory system in which the units in the memory system are reconfigurable both in size and in number. The decoder is designed to take an address for that memory system and address memory space in the memory system irrespective of the amount of storage in the system so that the decoder has to change as memory capacity is added or subtracted from the memory system.

Disclosed is a data transfer mechanism between the data bus of a data processing system and a data store. The data transfer mechanism includes common logic for converting between parity coded data on the data bus and error checking and correcting (ECC) coded data associated with the data store. Parity errors in data for presentation to the data store are detected, and single error correction and double error detection (SEC/DEC) syndrome bits are generated from the original ECC bits when data is ...

Binary logic is added to the binary logic normally utilized for the purpose of generating and decoding binary code combinations which reflect the order of use of a number of units, utilized in sequence, to thereby indicate the unit least recently used (LRU). Disclosed is the utilization of six binary bits which are updated in accordance with a sequence of use of four units to thereby indicate the least recently used one of the four units. In accordance with known LRU techniques, there are 24 val...

A fast synonym detection and handling mechanism is disclosed for a cache directory utilizing virtual addressing in data processing systems. The cache directory is divided into 2.sup.N groups of classes, in which N is the number of cache address bits derived from a translatable part of a requested logical address. The cache address is derived from a non-translatable part of the logical address which is used to simultaneously select one class in each of the 2.sup.N groups. The selected class entri...

A cache organization that enables many cache functions to overlap without extending line fetch or line castout time and without requiring a cache technology faster than the processor technology. Main storage has a data bus-out and a data bus-in, each transferring a double word (DW) in one cycle. Both busses may transfer respective DWs in opposite directions in the same cycle. The cache has a quadword (QW) write register and a QW read register, a QW being two DWs on a QW address boundary. During ...

A fast path (comprising control and data busses) directly connects between a storage element in a storage hierarchy and a requestor. The fast path (FP) is in parallel with the bus path normally provided through the storage hierarchy between the requestor and the storage element controller. The fast path may bypass intermediate levels in the storage hierarchy. The fast path is used at least for fetch requests from the requestor, since fetch requests have been found to comprise the majority of all...

In a shift register latch scan string such as that employed in level sensitive scan design (LSSD) methodologies, primary input and/or primary output signal line connections are distributed in a substantially uniform fashion along the length of the shift register scan string configuration so as to provide a mechanism for testing for fault conditions existing along the scan string.

The disclosure provides a plurality of embodiments for controlling the bus paths for a line of data from any cache in a multiprocessing system (MP) to any requesting cache or I/O channel processor in the MP. The data transfers can occur in parallel among plural CPU caches, channel processors and main storage (MS) sections using crosspoint switches in a manner which utilizes the high circuit count of LSI modules without substantially utilizing the module I/O pin count to enable MP structures to c...

A directory memory system having simultaneous writing and bypass capabilities. A data output bit from a respective memory cell of a memory array is applied to a control input of a first differential amplifier, while comparison input data is applied to inputs of a second differential amplifier. The outputs of corresponding transistors of the two differential amplifiers are connected together. Current switch transistors, operated in response to a bypass select signal, supply current only to one or...

Logic fencing circuit and method are provided for increasing system protection at a multiprocessor system interface so that spurious noise (e.g., attributable to an electrostatic discharge through a signal cable) is more reliably isolated from an active portion of the processing system. The noise fencing circuit, which is responsive to a fence control signal, includes logic circuitry for attenuating a received noise signal by constraining the noise signal to a magnitude less than or equal to the...