A method is described of detecting and correcting errors in a computer having a memory subsystem including a burst DRAM device. The method includes the steps of beginning a write operation of N data bits to the burst DRAM device, generating M check bits from the N data bits, writing the N data bits and the M check bits to the burst DRAM device, reading the N data bits and M check bits from the burst DRAM device, generating X syndrome bits from the N data bits and the M check bits, and using the ...

A computer system has a memory controller for controlling accesses to multiple memory modules, each having multiple memory blocks, and a fail-over circuit for failing-over individual memory blocks from multiple memory modules. The digital information stored in an individual memory block that has experienced memory errors in excess of a permissible threshold is copied to an auxiliary memory location. The memory accesses directed to the failed-over memory block are intercepted and redirected to th...

A computer system includes a processor bus having processor data and processor check bits for performing error detection and correction of the processor data. A CPU is coupled to the processor bus. A memory sub-system is coupled to the processor bus and includes memory check bits, memory address bits, and memory data bits, and an error detection and correction device for detecting an error in the memory address bits using the memory check bits and for detecting an error in the memory data bits u...

A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to wo...

A computer system with a bus arbitration system adaptively assigns priority to devices on the bus based upon workload. A bus arbiter receives request signals from bus devices that require bus access, and also receives a signal indicating the pending workload of that device, as measured by the number of operations pending in a queue in that device. Based on the workload signal, the bus arbiter breaks any arbitration conflicts by assigning priority to the device with the greatest workload. In the ...

A core logic chipset for a computer system is provided which can be configured as a bridge between either an accelerated graphics port (AGP) bus or an additional peripheral component interconnect (PCI) bus. A common bus having provisions for the PCI and AGP interface signals is connected to the core logic chipset and either an AGP or PCI device(s). The common bus, which is part of a fault-tolerant interconnect system, includes a first bus portion and a lower bus portion. When an error (e.g., a p...

A fail-over system for memory is provided. The fail-over system for memory includes a virtual channel memory controller providing one or more virtual channel memories in a memory array. A memory fail-over controller coupled to the virtual channel memory controller provides memory fail-over data to the virtual channel memory controller. The virtual channel memory controller allocates one or more of the virtual channel memories to one or more fail-over memory channels in response to the memory fai...

A computer system has a memory controller for controlling accesses to multiple memory modules, each having multiple memory blocks, and a fail-over circuit for failing-over individual memory blocks from multiple memory modules. The digital information stored in an individual memory block that has experienced memory errors in excess of a permissible threshold is copied to an auxiliary memory location. The memory accesses directed to the failed-over memory block are intercepted and redirected to th...

A technique for handling errors in a memory system. Specifically, a new dual mode ECC algorithm is provided to detect errors in memory devices. Further, an XOR memory engine is provided to correct the errors detected in the dual mode ECC algorithm. Depending on the mode of operation of the dual mode ECC algorithm and the error type (single-bit or multi-bit), errors may be corrected using ECC techniques. If X16 or X32 memory devices are implemented, a technique for striping the data from each mem...

A cache system for multiple processors including multiple caches, one of the caches serving each respective processor, a main memory system, and a bus interconnecting the caches and the main memory, the bus allowing data to be written directly between the caches without accessing the main memory system.