A check system for checking a comparison check function of an information processing apparatus which includes first and second microprocessors includes a check part for supplying mutually different data to the first and second microprocessors when checking the comparison check function, and a comparing part for comparing data which are output from the first and second microprocessors in response to the mutually different data supplied to the first and second microprocessors. The comparing part g...

In a multi-processor system in which a plurality of units such as a CPU serving as an information processing unit and an I/O control unit can be connected over a system bus, when the plurality of units issue use requests for the system bus, a bus arbiter grants a use authority for the system bus to a specific unit in consideration with priority orders. The bus arbiter is connected to the respective units over at least one specific signal line. The specific signal line conforms to a specific tran...

In a bus arbiter connected to a system bus of a multi-processor system having a plurality of modules respectively having processors, a first unit detects an abnormality in the multi-processor system on the basis of an internal state of the bus arbiter and a predetermined signal transferred via the system bus. A second unit initializes the internal state of the bus arbiter to restart the bus arbiter when the first unit detects an abnormality.

When a unit connected to a data transfer bus on which data transfer is controlled synchronously with a bus cycle makes a request for using the bus, permission is granted to one of the units which have made the request. The permission to use the bus is switched over at a bus cycle when data transfer is completed in the unit. Consequently, the bus cycle can be shortened, and the speed of the data transfer by the bus can be increased. To achieve this, the unit which has granted permission to use th...

The present invention provides a cache-data transfer system improving a cache-hit rate by making a block size of the external cache memory longer than the block size of an internal cache memory. The system makes a block size of the external cache memory longer than a block size of the internal cache memory by inserting a data transfer process which transfers a data from the storage means to only the external cache memory during a data transfer process from the storage means to the internal cache...

There is provided a data synchronization circuit for synchronizing a (n+1) (n: natural number) bit bus data synchronous with a first clock with a second clock, comprising: a first circuit for holding the bus data which is synchronous with the first clock and is input at each predetermined timing; a second circuit for generating a first timing signal which is synchronous with the first clock and is corresponding to the predetermined timing; a third circuit for generating a second timing signal wh...

A message control system for a data communication system in the form of a loosely coupled multiprocessing system, in which a plurality of processing modules having a memory unit are coupled to each other via a system bus. In this message control system, a memory unit, within each processing module, includes a data processing part which is in software running on a central processing unit within its own processing module, a descriptor which manages address and data length information of a storage ...

An asynchronous access system includes a system bus, at least one processing module provided with a main memory, a central processing unit and a first connection unit which connects to the system bus, and at least one shared memory module provided with a shared memory unit and a second connection unit which connects to the system bus. The first connection unit within the processing module makes a block read request to the shared memory module via the system bus when the first connection unit rec...

In an asynchronous access system for a multiprocessor system having a plurality of processor modules connected to a system bus and at least one shared memory module connected to the system bus, each of the processor modules includes a processor and an internal buffer. The processor writes data into the internal buffer, and the data is read from the internal buffer and is written into the shared memory via the system bus. The asynchronous access system includes a first unit, provided in each of t...

A magenta toner is provided which contains at least a binder resin, a colorant, and a wax, in which a maximum heat-absorption peak temperature as measured using a differential scanning calorimeter, a reflectance at a predetermined wavelength when measured in a powder state by spectroscopic analysis, and lightness when measured in a powder form are in specific ranges. A full-color image is formed using the magenta toner as a pale magenta toner in combination with a deep magenta toner. According t...