A computer system in which each of certain critical instructions, all performing multiple main storage accesses to shared data, have the appearance of executing required main storage accesses atomically with respect to a predefined set or class of instructions. The instructions in each set, referred to as relatively atomic instructions, are grouped together based on the data structure or object class they affect. The computer system comprises: (a) shared memory means; (b) a plurality of processo...

In a first aspect, a first method is provided for removing entries from an address cache. The first method includes the steps of (1) writing data to a register; and (2) removing a plurality of address cache entries from the address cache based on the data written to the register. Numerous other aspects are provided.

Addressing control apparatus is structured to provide either byte or word addressing of storage organized on a word basis. The storage address register is made shiftable whereby for byte operations, it is shifted, and the bit shifted out of the register is used for byte selection. The contents of the storage address register are used to address storage for both word and byte addressing, and no change is required. The storage access, however, for byte addressing takes place after the shift is com...

A computer for implementing a method for conditionally capturing hardware scan dump data to minimize the reboot recovery time employs a service processor operable to detect a failure of another hardware component of the computer. Upon detection, the service processor will conditionally capture hardware scan dump data. The first condition for capturing hardware scan dump data is the service processor being activated into an active storing mode of operation labeled "Always". The second condition f...

A method handles concurrent address translation cache misses and hits under those misses while maintaining command order based upon virtual channel. Commands are stored in a command processing unit that maintains ordering of the commands. A command buffer index is assigned to each address being sent from the command processing unit to an address translation unit. When an address translation cache miss occurs, a memory fetch request is sent. The CBI is passed back to the command processing unit w...

A memory controller, upon detecting an interval of inactivity (that is, no read or write access from a processor or I/O devices with respect to main storage or memory SDRAMs) halts external refresh commands from the processor, and initiates STR mode in main storage to preserve data contents in the memory SDRAMs and to save energy. Then, upon detecting a read or write operation, the memory controller signals main storage to exit STR mode.

The data processing system includes a plurality of execution units forming a plurality of processing pipelines. The plurality of processing pipelines process instructions and include a storage pipeline. The data processing system further includes an instruction unit and a storage control unit. The instruction unit outputs instructions to the plurality of execution units, and controls execution of multiple threads by the plurality of execution units. If an instruction for a first thread in the st...