Abstract of
GB971359
971,359. Telegraphy. LENKURT ELECTRIC CO. Inc. June 11, 1963 [July 2, 1962; Dec. 17, 1962; Jan. 30, 1963], No. 23174/63. Heading H4P. In a limited bandwidth data transmission system binary data is converted to a 3-level signal, whereby the data may be sent faster than would be possible in binary form. The signal is such that adjacent pulses are in adjacent levels or in the same level, and is reconverted at the receiver. Transmitting arrangements.-Binary signals, e.g. 13, Fig. 4, are fed to gate 11 which, whenever a clock pulse and a mark are present, triggers unit 12. The output of this is therefore as waveform 14. This waveform is fed to an adder both direct and via a 1 bit delay. The resultant waveform is filtered by the transmission equipment, waveform 16, and sent by A.M., F.M., or P.M. line or radio path to the receiver. The waveform 16 is regarded as a 3-level signal, the levels being as indicated. Receiving arrangements.-In one embodiment, Fig. 5, the received signal is fed to slicing circuits which provide waveforms 21A, 21B, Fig. 4, representing the upper and lower levels of the signal. These waveforms are fed to gate 22 as shown, together with clock pulses. Whenever gate 22 pulses, unit 24 provides a mark pulse. A second gate 23, fed as shown, causes unit 22 to provide a space. The output of unit 22 is the re-converted waveform 13. A second embodiment, Fig. 6 (not shown), converts the received signal 16 to waveform 14 before reconstituting the binary data 13. In a further embodiment the transmitted waveform 16<SP>1</SP>, Fig. 9, is passed through a fullwave rectifier to give waveform 18<SP>1</SP>. This wave form, after squaring, is the reconstituted data. If the waveform has jitter it is stabilized by the circuit of Fig. 11 (not shown). Error detection.-It is inherent in the conver sion of the binary data that when a pulse in level 1 or 2 is followed by an even number of adjacent middle level pulses the next pulse will also be in the level 1 or 3, respectively, whereas if it is followed by an odd number of middle level pulses the next pulse will be in level 3 or 1, respectively. Thus an error detecting arrangement can be constructed, as in Fig. 13 (not shown), which will predict the pulse to be received after one or more middle level pulses. There may be included with the detector a counter which is periodically reset and, for example, causes repetition of a block of data if too many errors are counted. Alternative arrangement.-The binary signals are fed direct to the delay-and-adder circuit, Fig. 1A (not shown), the transmitted signal then being as waveform 42, Fig. 8. The data is reconstituted by the circuitry of Fig. 7 (not shown).
Appareil de transmission électrique d'informations binaires par un canal de communication à largeur de bande de fréquence limitée
Inventor:
Applicant: LENKURT ELECTRIC CO INC
EC:H04L25/497
IPC: H04L25/48; H04L25/497;H04L25/40(+1)
Publication info: FR1366276 A - 1964-07-10
5
High speed data transmission system
Inventor:
Applicant:
EC:H04L25/497
IPC: H04L25/48; H04L25/497;H04L25/40(+1)
Publication info: GB971359 A - 0000-00-00
6
High speed data transmission system
Inventor:
Applicant:
EC:H04L25/497
IPC: H04L25/48; H04L25/497;H04L25/40(+1)
Publication info: NL294752 A - 0000-00-00
7
High speed data transmission system
Inventor: LENDER A (US); DOTTER B (US)
Applicant: LENKURT ELECTRIC CO INC (US)
EC:H04L25/497
IPC: H04L25/48; H04L25/497;H04L25/40(+2)
Publication info: SE320999 B - 1970-02-23
8
High speed data transmission system
Inventor: ADAM LENDER
Applicant: AUTOMATIC ELECT LAB
EC:H04L25/497
IPC: H04L25/48; H04L25/497;H04L25/40(+1)
Publication info: US3234465 A - 1966-02-08
9
High-speed data transmission system
Inventor: ADAM LENDER
Applicant: AUTOMATIC ELECT LAB
EC:H04L25/497
IPC: H04L25/48; H04L25/497;H04L25/40(+1)
Publication info: US3238299 A - 1966-03-01
10
Error detection in duobinary data systems
Inventor: DOTTER JR BERTON E
Applicant: AUTOMATIC ELECT LAB
EC:H04L25/497
IPC: H04L25/48; H04L25/497;H04L25/40(+1)
Publication info: US3303462 A - 1967-02-07
List of citing documents
1
DOUBLE DENSITY CODE ERROR DETECTION
Inventor: CSENGERY LADISLAO CHUMEY
Applicant: LOCKHEED ELECTRONICS CO
EC:G11B20/14A2; H04L1/24D1
IPC: G11B20/14; H04L1/24;G11B20/14(+3)
Publication info: GB2126849 - 1984-03-28
Claims
WHAT WE CLAIM IS:
1 Apparatus for the transmission of binary data over a transmission channel of limited frequency bandwidth, which comprises: means for supplying to the transmission channel electric pulses representing binary data to be transmitted at a bit rate up to about four times the frequency bandwidth limit of said channel, whereby an electric signal is received having three detectable amplitude zones consisting of an inner zone and two outer zones, the maximum change in amplitude of said received signal during a one-bit interval being from one of said three zones to an adjacent one of said three zones, detecting means for determining the amplitude zone within which the amplitude of said received signal lies, and means for reconstructing said electric pulses from the output of said detecting means.
2 The apparatus of Claim 1 wherein the output of said reconstructing means is a signal alternately representing opposite binary states when said detecting means indicates that the amplitude of the received signal is in said inner amplitude zone; the output of said reconstructing means is a signal representing one binary state when said detecting means indicates that the amplitude of the received signal is in one of said two outer amplitude zones; and the output of said reconstructing means is a signal representing the other binary state when said detecting means indicates that the amplitude of the received signal is in the other of said two outer amplituded zones.
3 The apparatus of Claim 1 wherein said detecting means includes a pair of slicers.
4 The apparatus of Claim 3 wherein said reconstructing means includes: a first AND-gate having an input connected to one of said pair of slicers, and an output connected to the SET input of a flipflop, a second AND-gate having an input connected through an inhibitor to the other of said pair of slicers and an output connected to the RESET input of said flip-flop, and a third AND-gate having an input connected through an inhibitor to said one of said pair of slicers, an input connected to said other of said pair of slicers, and an output connected to the COMPLEMENT input of said flip-flop.
Apparatus for transmitting a waveform of electric pulses representing binary data over a transmission channel of limited bandwidth comprising means for converting said waveform, incident to transmission over said channel, into a different waveform of electric pulses having three detectable amplitude zones comprising an inner zone and two outer zones, a maximum change in amplitude from one pulse to the next adjacent pulse of said converted waveform being from one of said three zones to an adjacent zone, and two successive outer-zone pulses in said converted waveform being in the same outer zone if said outer-zone pulses are separated by an even number of inner-zone pulses but being in opposite outer zones if separated by an odd number of inner-zone pulses.
6 Apparatus as claimed in Claim 5, characterised in that the bit rate of said binary data is up to four times the frequency bandwidth limit of said channel.
7 Apparatus as claimed in Claim 5 or 85 6 in which differentiating means are provided at the sending end of said channel for digitally differentiating said first-mentioned electric pulses.
8 Apparatus as claimed in Claim 7, 90 characterized in that said differentiating means includes an AND-gate having one input from the source of said electric pulses and another input from a clock pulse generator, and a flip-flop having its complement 95 input connected to the output of said ANDgate, the output of said flip-flop supplying the digitally differentiated pulses.
9 Apparatus as claimed in Claim 7 or 8, characterised in that siad differentiating 100 means is disposed on the input side of the transmission equipment at the sending end of said channel, said transmission equipment including a low-pass filter having a cut-off frequency of about one fourth the bit rate 105 of said binary data.
Apparatus as claimed in Claim 7 or 8, comprising means at the sending end of said channel for arithmetically summing the differentiated pulses with themselves de 110 layed by a one-bit duration.
11 Apparatus as claimed in any preceding claim comprising means for reconverting the received waveform into a waveform having a series of pulses of two discrete ampli 115 tude levels, said last-mentioned means comprising discriminating means for discriminating between outer-zone and inner-zone pulses of said received waveform.
12 Apparatus as claimed in Claim 11, 120 characterised in that said discriminating means includes a pair of slicers, one slicer of said pair being for detecting pulses in one of said outer zones of said converted waveform and the other slicer being for detect 125 ing pulses in the other outer zone of said waveform.
13 Apparatus as claimed in Claim 11 or II I i 12, comprising circuitry connected to the output of said discriminating means for reconverting the received waveform directly into one corresponding to the original binary pulses, said circuitry providing binary pulses of said one level in response to the detection of received pulses of either outer zone, and providing pulses of said other level in response to the detection of received pulses of said inner zone.
14 Apparatus as claimed in Claim 13, characterised in that said circuitry includes a first AND-gate having a first input connected to one of said pair of slicers, a IS second input connected through an inhibitor to the other of said pair of slicers, and an output connected to the SET input of a flipflop; a second AND-gate having an input connected through an inhibitor to the output of said first AND-gate and an output connected to the RESET input of said flipflop; both of said AND-gates having an input connected to a pulse synchronising means.
Apparatus as claimed in Claim 11 or 12 comprising first circuit means connected to the output of said discriminating means for converting the received waveform into a waveform corresponding to said digitally differentiated pulses and second circuit means connected to the output of said first circuit means for converting the last-mentioned waveform into one corresponding to the original binary pulses.
16 Apparatus as claimed in Claim 15, characterised in that the output of said first circuit means is a signal alternately representing opposite binary states when said discriminating means indicates that the amplitude of the receive signal is within said inner zone; that the output of said first circuit means is a signal representing one binary state when said discriminating means indicates that the amplitude of the received signal is within one of said two outer zones; and that the output of said first circuit means is a signal representing the other binary state when said discriminating means indicates that the amplitude of the received signal is within the other of said two outer zones.
17 Apparatus as claimed in Claim 15 or 16, characterised in that said first circuit means includes a first AND-gate having an input connected to one of said pair of slicers and an output connected to the SET input of a first flip-flop; a second AND-gate having one input connected through an inhibitor to said one of said pair of slicers, a second input connected to the other of said pair of slicers, and an output connected to the COMPLEMENT input of said first flip-flop; and a third AND-gate having an input connected through an inhibitor to said other of said pair of slicers and an output connected to the RESET input of said first flip-flop, all of said AND-gates having an input connected to a pulse synchronlising means.
18 Apparatus as claimed in Claim 16 or 17, characterised in that the output of said second circuit means is a signal indicating one binary state when the output of 70 said first circuit means is a signal indicating the opposite binary state from the previous signal; and that the output of said second circuit means is a signal indicating the other binary state when the output of said first cir 75 cuit means is a signal indicating the same binary state as the previous signal.
19 Apparatus as claimed in Claim 18 characterised in that said second circuit means includes a second flip-flop having an 80 input connected to the output of said first flip-flop; a fourth AND-gate having an input connected through an inhibitor to the output of said second flip-flop, an input connected to the output of said first flip-flop, 85 and an input connected to a pulse synchronising means; a fifth AND-gate having an input connected to the output of said second flip-flop, an input connected through an inhibitor to the output of said flip-flop and an 90 input connected to said pulse synchronising means; an OR-gate having an input connected to the outputs of each of said fourth and said fifth AND-gates and an output connected to the SET input of a third flip 95 flop; and a sixth AND-gate having an input connected through an inhibitor to the output of said OR-gate, an input connected to said pulse synchronising means, and an output connected to the RESET input of said third 100 flip-flop.
Apparatus as claimed in Claim 11, characterised in that said discriminating means is connected to the output of rectifying means for rectifying the received wave 105 form, whereby the portion of said received waveform which lies in one of said two outer zones is transferred to the other outer zone, thereby producing a resulting electric signal having only two amplitude zones one of 110 which is said inner zone and other of which is said other outer zone.
21 Apparatus as claimed in Claim 20, characterised in that said rectifying means is a full-wave rectifier 115 22 Apparatus as claimed in Claim 20 or 21, characterised in that said discriminating means is a single slicer.
23 Apparatus as claimed in any of Claims 20 to 22, characterised in that re 120 timing means are connected to said discriminating means for removing time jitter from the detected signal.
24 Apparatus as claimed in Claim 23, characterised in that said retiming means 125 includes: a first AND-gate having a first input connected to the output of said discriminating means, a pulse synchronising means connected to a second input of said first AND-gate, a flip-flop having one of its 130 971,359 971,359 SET and RESET inputs connected to the output of said first AND-gate, and a second AND-gate having an input connected through an inhibitor to the output of said first AND-gate, having another input connected to said pulse synchronising means, and having an output connected to the other of said SET and RESET inputs of said flipflop.
25 Error detecting apparatus for detecting errors in operation of apparatus as claimed in any preceding claim comprising counting means for determining if the number of successive inner zone pulses in any 13 pulse series of said received waveform is even or odd, whereby the output of said counting means continuously predicts whether the next following outer zone pulse will be in the one or the other outer zone; detecting apparatus having an output indicating whether each outer zone pulse, as it occurs, actually is in the one or the other zone, and means for comparing said output of the counting means with said output of 23 the detecting apparatus and causing an error indication to be given when the output of said counting means fails to agree with the output of said detecting apparatus.
26 Apparatus as claimed in Claim 25, characterised in that said counting means comprises a binary counter, and that a coupling is provided between the output of said comparing means and the input of said counter so that, upon detection of an error, the state of said counter is automatically reversed and the counter thereby brought in phase with subsequent transmission.
27 Error detecting apparatus as claimed in Claim 25 or 26 in combination with apparatus of any one of Claims 12 to 24, characterised in that each said slicer has two outputs, the first indicating that a detected pulse is in the corresponding outer zone and the second indicating that it is not, and that coincidence means are interposed between said second outputs of said slicers and the input of said counter means, said coincidence means providing an output when neither of said slicers detects an outer zone pulse, the last-mentioned output thereby indicating an inner zone pulse.
28 Apparatus as claimed in Claim 27 characterised in that said binary counter comprises a flip-flop and a second output indicating the other state, that said comparing means comprises a first and a second AND-gate and an OR-gate connected to the outputs of said AND-gates, said first ANDgate having an input from said first output of said flip-flop and another input from said first output of the other slicer; and that error indicating means are connected to the output of said OR-gate.
29 Apparatus as claimed in Claim 27 or 28, characterised in that an OR-gate is interposed between the output of said coincidence means and the input of said flipflop, said OR-gate having another input connected to the output of said first-mentioned OR-gate to provide said automatic reversal of the state of said flip-flop.
Apparatus as claimed in Claim 28 or 29 characterised in that said error indicating means comprises a step-counter for counting the number of indicated errors within a predetermined time period, said stepcounter providing an output signal in the event the number of errors exceeds a predetermined number within said time period.
31 Apparatus for the transmission of binary data over a transmission channel of limited frequency bandwidth, constructed, arranged and adapted to operate substantially as hereinbefore described with reference to Figure(s) 1, 1 A, 2, 3, 5, 6, 7 and 8, 9, 10, 11 or 13.
GEE & CO, Chartered Patent Agents, 51/52 Chancery Lane, London, W C 2, and 22 Whitefriargate, Hull, Agents for the Applicants.
a Abingdon: Printed for Her Majesty's Stationery Office, by Burgess & Son (Abingdon), Ltd -1964.
Published at The Patent Office, 25 Southampton Buildings, London, W C 2, from which copies may be obtained.
U j I
Description
PATENT SPECIICATION
DRAWINGS ATTACHED.
971359 Date of Application and filing Complete Specification:
June 11, 1963 No 23174/63.
Application made in United States of America (No 206,747) on July 2, 1962.
Application made in United States of America (No 245,324) on Dec 17, 1962.
Application made in United States of America (No 255,127) on Jan 30, 1963.
Complete Specification Published: Sept 30, 1964.
) Crown Copyright 1964.
Index of Acceptance:-H 4 P( 16 G 1 D, 31).
International Classification:-H 041.
COMPLETE SPECIFICATION.
Improvements in or relating to Data Systems.
We, LENKURT ELECTRIC CO, INC, of 1105 County Road, San Carlos, California, United States of America, a Corporation organized and existing under the laws of the State of Delaware, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:-
This invention relates to apparatus for the electrical transmission of binary data over a communications channel of limited frequency bandwidth More specifically, the invention provides a means of transmitting binary data at twice the bit rate previously believed maximum using a conventional binary method In spite of this substantial increase in transmission rate, the original binary data can be unambiguously reconstructed from the signal at the receiving end.
It is well known in the art that the maximum transmission rate over a transmission channel of limited bandwidth is set by Nyquist's rule For binary data, C= 2 f where C is the maximum transmission rate in bits per second and f is the frequency bandwidth limit of the system All data communication systems have a frequency bandwidth limit This sometimes arises in the sending equipment, the receiving equipment, the transmitting equipment, or the transmission medium It is almost always desirable to transmit the most possible data in the available frequency bandwidth A higher bit rate is possible with conventional systems if the data is coded in a number system with a base greater than 2 With quaternary data, for example, C= 4 f Many communication systems, therefore, use the quaternary base in order to double the transr D; e i X mission rate However, the resultant increase in transmission speed is paid for by concomitant disadvantages First, quaternary systems are considerably more sensitive to noise This causes a larger number of errors with a given noise level Second, the complexity of the transmission equipment for a quaternary system is approximately doubled.
This invention provides new apparatus for a binary data communication system which permits a maximum transmission speed twice that heretofore thought possible for binary data by Nyquist's rule The maximum bit speed in this invention is therefore the same as previously possible only with a quarternary system Yet the sensitivity to noise is 3 6 db less than in a quaternary system; and the complexity of the equipment required in a preferred embodiment of the invention is about the same as in a conventional binary system-about half that of a quaternary system Additionally, the intersymbol interference is substantially less than that in a quaternary system.
According to the invention, apparatus for the transmission of binary data over a transmission channel of limited frequency bandwidth comprises means for supplying to the transmission channel electric pulses representing binary data to be transmitted at a bit rate up to about four times the frequency bandwidth limit of said channel, whereby an electric signal is received having three detectable amplitude zones consisting of an inner zone and two outer zones, the maximum change in amplitude of said received signal during a one-bit interval being from one of said three zones to an adjacent one of said three zones, detecting means for determining the amplitude zone within which I -, I I the amplitude of said received signal lies, and means for reconstructing said electric pulses from the output of said detecting means.
Also according to the invention, apparatus for transmitting a waveform of electric pulses representing binary data over a transmission channel of limited bandwidth comprises means for converting said waveform, incident to transmission over said channel, into a different waveform of electric pulses having three detectable amplitude zones comprising an inner zone and two outer zones, a maximum change in amplitude from one pulse to the next adjacent pulse of said converted waveform being from one of said three zones to an adjacent zone, and two successive outer-zone pulses in said converted waveform being in the same outer zone if said two outer-zone pulses are separated by an even number of inner-zone pulses but being in opposite outer zones if separated by an odd number of inner-zone pulses.
Briefly, the apparatus of this invention includes a means for supplying to the transmission channel electric pulses representing binary data to be transmitted at a bit rate of up to about four times the frequency bandwidth limit of the transmission channel.
Because the data waveform at such a high bit rate relative to the bandwidth of the transmission channel contains essential frequency components which the transmission channel is incapable of transmitting, the data waveform is not transmitted through the channel in its original form Nevertheless, there will be a received signal from which the original data can be reconstructed, in accordance with this invention.
Although not essential to the invention, an improvement in signal-to-noise ratio and greater flexibility in transmission bit rate may be obtained by including an arithmetical summer in the pulse supply Such a summer adds the data pulse waveform to a second waveform which is identical in shape to the original, but delayed by one bit In this fashion the transmitted signal is converted to the shape in which it is to be received before it is passed through the transmission medium Although the addition of the arithmetical summer would, at first glance, appear to add equipment to the sys5) tern, in actual practice the overall expense may be reduced, because the summer substantially lessens the critical tolerances imposed on later equipment in the system In general, any tolerance reduction results in a decrease in manufacturing cost.
The received signal has three detectable amplitude zones These consist of two outer zones and an inner zone The maximum change in signal amplitude during a 6 one-bit time interval is from one of the three amplitude zones to an adjacent one of the three zones Thus, the received signal is not ternary-a ternary signal also has three amplitude levels, buwt it can vary among any of the three during one pulse duration Fur 70 thermore, the apparatus of the invention requires no special conversion apparatus to obtain the received signal Such apparatus would be required if the data were converted from binary to ternary In the receiving 75 apparatus, according to this invention, means are provided for determining within which of the three amplitude zones the amplitude of the received signal lies, and for reconstructing the electric pulses representing the St original binary data from the output of the detecting means In a preferred embodiment of the invention, the detecting means must determine only whether the amplitude of the received signal is in the inner zone From 85 this one strictly binary decision, the data input waveform can be Unambiguously reconstructed In this preferred embodiment of the invention, there is no memory in the data detection and reconstruction apparatus 90 All binary decisions are based on a single pulse This eliminates any multiplication of errors which results from a system which must make logical decisions based upon more than a single pulse 95 A retiming circuit may be used in the detection and reconstruction portion of the system; however, it is a very important feature of a modification, described later herein, of the system according to the invention, 100 that such a circuit is not essential, and is not used, in a very large number of applications The system first disclosed in the following description requires a retiming circuit With the later-described modification 105 retiming is not needed when the amount of time jitter due to transmission distortion is small compared to the bit duration Moreover, in transmission of the kind known in the art as "Teletype" (Registered Trade 110 Mark), where the synchronization is an integral function of the start and stop signals, retiming is unnecessary.
One advantage of eliminating the retiming circuit is that the clock pulse generator (in 115 the detection and reconstruction portion of the apparatus) is eliminated There is, however, another advantage even more important, although less immediately apparent Bit speed in the transmitter is forever limited 120 by the speed of a clock pulse generator in the receiver Substantial modification of the receiver is necessary before bit speed of transmission can be modified The receiver according to the aforementioned modi 125 fication where no retiming circuit is used can accept signals transmitted at any bit speed within the operating range of the invention This characteristic adds a very useful flexibility to the system 130 971,359 971,359 Substantially any conventional carrier transmission or baseband equipment may be used Specific examples of carrier systems include AM, FM, and phase-modulation.
The apparatus of the invention may be applied to "Tele'ype" systems to double the nuiimber of transmission channels while still using the same frequency bandwidth Telemetry applications are also possible.
The apparatus of this invention is perfectly compatible with conventional binary data transmission channels It can be used with presently available transmission equipment, for example, pulse code modulation (PCM) equipment, without the need for major changes in either the transmission channel or in the regenerative repeaters installed in the transmission lines Furthermore, the system provides a balanced signal.
There are no d-c or low-frequency signal components so that transformers may be used without difficulty.
The invention may be better understood from the more detailed description which follows, referring to the drawings in which:Fig 1 is a block diagram of one embodiment of the invention; Fig IA is a block diagram of another embodiment; Fig 2 is a block diagram of another embodiment comprising FM transmission apparatus; Fig 3 is a block diagram of a conventional digital differentiator; Fig 4 shows a binary data waveform at various stages of the transmission using apparatus of a preferred embodiment of the invention; Fig 5 shows a data detector and reconstructor of a preferred embodiment of the invention; Fig 6 is a block diagram of a data detector and reconstructor of another embodiment of the invention; Fig 7 is a block diagram of a data detector and reconstructor of still another embodiment of the invention; and Fig 8 shows a binary data waveform in various stages of transmission using the embodiment of the invention shown in Fig 7; Fig 9 shows a binary data waveform at various stages of transmission using apparatus according to a further embodiment of the invention; Fig 10 shows a data detector and reconstructor of this further embodiment of the invention which requires no clock; and Fig 11 shows a data detector and reconstructor of yet another embodiment of the invention.
Fig 12 is a graph showing an illustrative waveform of data transmitted by the system according to this invention including an error; and Fig 13 is a schematic circuit diagram of error detection apparatus that may be used in accordance with this invention.
Referring to Fig 1, binary data is generated by a data source input l The data 70 source used for the invention is conventional.
However, the bit rate of the data entering the transmission equipment can be up to about four times the frequency bandwidth limit of the system This rate is twice that 75 previously possible for a conventional binary system, and is equal to that previously possible using a quaternary system Somewhere in the transmission system there is invariably an inherent frequency bandwidth 80 limitation.
In baseband transmission systems, a lowpass filter is invariably used in the transmitter The bandwidth of this filter determines the system bandwidth, and therefore the 85 maximum possible bit rate in carrier transmission systems, on the other hand, such a low-pass filter before the carrier modulation equipment is not always used, but a bandpass filter must be employed following the 90 carrier modulator However, since a carriermodulated signal has two sidebands, the bandwidth of this bandpass filter must be twice that of a low-pass filter located before the carrier modulation equipment in the 95 system Therefore the maximum bit rate, calculated as a function of this double-sized bandpass filter, is twice that bandwidth rather than four times.
With the apparatus of the invention, a 100 reconstrucible signal can be transmitted at a bit rate up to about four times this frequency bandwidth limit; although four is not an absolute limit, the error rate becomes too high above 4 5 times the bit rate, 105 for example If the bit rate falls below about four times the bandwidth, a conventional lowpass filter is used The cut-off frequency of the filter is about one-fourth the bit rate Therefore the system of this 110 invention is perfectly compatible for bit speeds below twice the frequency bandwidth limit as well as above that speed up to about four times the frequency bandwidth limit.
In most applications, a maximum transmis 115 sion speed is desirable Therefore in practice the system of this invention is operated at its most desirable bit rate of about four times the frequency bandwidth limit.
In the embodiment shown in Fig IA, the 120 transmission speed may be varied at will anywhere within the range of the invention, because conversion to the output waveform occurs before the signal encounters the lowpass filter in the transmitter (The output 125 waveform is shown, for example, as waveform 16 in Fig 4) This conversion is performed by flip-flop la and arithmetical summer lb An arithmetical summer is merely a pair of resistors connected together at the 130 I output; the two inputs are connected to the unconnected ends of the resistors.
The embodiment illustrated in Fig IA has yet another advantage It reduces interS symbol interference, thereby increasing the signal-to-noise level ratio of the receiver.
The transmission equipment 2 is not a part of the invention In the block 2 designated as transmission equipment, both the transmission medium and the linear carrier modulation equipment (if any) are included.
This equipment is used to transmit the data pulses from the data source 1 to the data detector and reconstructor 3 The simplest 1.5 baseband data transmission system, of course, is a cable Cables have limited bandwidth which fixes the maximum bit speed.
If desired, the data may be carrier-modulated Because linear modulation systems are well known in the art, it is not necessary to go into them in detail here Amplitude modulation, frequency modulation, phase modulation (either analog or coherent digital), or other methods of carrier modulation may be used A specific example of one type of carrier modulation and transmission equipment, FM, is shown in Fig 2.
Referring to Fig 2, electric pulses from the data source enter the frequency shift key 4 The frequency shift key may be a single oscillator, keyed in a strictly binary manner by switching a fixed capacitor in or out This shift key effectively shifts between two fixed frequencies according to whether the signal is in one or the other of the two binary states These two binary states will be referred to as MARK and SPACE The binary-keyed wave emitted from the frequency shift key 4 is applied to a transmitter bandpass filter 5 The signal from the transmitter bandpass filter 5 is sent across a transmission medium 6 (which may be a cable, h-f radio, etc,) to the receiver.
The receiver bandpass filter 7, the limiter amplifier 8, the discriminator 9 and the lowpass filter 10 perform linear demodulation.
The wave shape of the pulse emitted from the lowpass filter 10 is the same as it would have been if there had been a cable with the same frequency bandwidth as the lowpass filter between the data source and the output of lowpass filter 10.
The system of this invention is particularly attractive for pulse-code modulation (PCM) baseband transmission The frequency spectrum of the transmitted pulses has no d-c or low-frequency components; therefore the system of the invention is compatible with many forms of existing PCM equipment For example, regenerative repeaters now used in conventional PCM transmission need only minor modification to be used for the system of this invention The total amount of equipment required for the apparatus of the invention is little more than is presently needed for PCM transmission, yet a transmission speed approximately twice that possible using straight binary PCM is made possible 710 In the preferred embodiment of the invention, the data waveform from the data source is passed through a digital differentiator before transmission A typical digital differentiator block diagram is shown in Fig 3 75 When a MARK appears from the data source, gate I has an output; otherwise it does not An output of gate 11 complements flip-flop 12; as a result, flip-flop 12 changes state only when a MARK appears 80 from the data source The data waveform is converted from the waveform 13 shown in Fig 4 to waveform 14 Waveform 14 emerging from flip-flop 12 has been digitally differentiated It has been surprisingly dis 85 covered that the complexity of the required data detector and reconstructor can be greatly reduced if the data is first passed through a digital differentiator before transmission Furthermore, a substantial increase 90 in reliability is obtained when a digital differentiator is used This will be explained later.
The use of a pulse synchronizing means, such as clock pulse generator 15 shown in 95 Fig 3 is conventional The clock pulse generator is a synchronization recovery circuit set to generate pulses at fixed frequency equal to the bit rate The clock pulses are phased with the signal using a conventional 100 synchronization circuit Clock pulse generators and synchronization circuits are described in Wier, J M, Digital Data Cornmunication Techniques, proceedinss of the IRE, Vol 49, January 1961, pp 196-204 105 The digitally differentiated pulse is transmitted in one of the ways described earlier.
A data detector and reconstructor of the preferred embodiment of this invention is shown in Fig 5 The waveform 16 shown in 110 Fig 4 is received from the transmission equipment It has three amplitude zones:
an inner zone and two outer zones, as shown.
The inner zone is the area between two slicing levels For optimum accuracy of 115 detection and reconstruction, the upper slicing level is set midway between the maximum and the center values of the amplitude of waveform 16 The lower slicing level is set midway between the minimum 120 and the center values of the amplitude of waveform 16 Although the slicing levels may vary somewhat from optimum, the reliability of the detector and reconstructor is lessened as these levels depart from 125 optimum.
Waveform 16 is passed through a pair of slicers 17 and 18 which are set at the desired slicing levels discussed above The output waveforms from the slicers appear at 130 971,359 waveform 16 lies in the inner zone, then AND-gate 22 has an output Flip-flop 24 is then SET, indicating a MARK Thus the data detector and reconstructor of Fig 5 detects the data from waveform 16 and 70 directly reconstructs the data of waveform 13.
Except for having two slicers rather than one, the data detector and reconstructor of this preferred embodiment requires no more j equipment than a conventional binary data detector and reconstructor, yet it can unambiguously reconstruct data transmitted at a rate twice that possible with the conventional binary system SO This preferred embodiment of the invention has other very important advantages.
The data detector and reconstructor has no memory Each binary decision is made strictly on the basis of a single pulse Where 85 decisions must be made on the basis of previous pulses, as well as the single pulse being detected, a multiplication of errors can result, i e, an error from previous pulses is repeated With the embodiment shown in 90 Fig 5, there is no such multiplication.
Another important advantage is obtained when the data detector and reconstructor of Fig 5 is used with a phase-modulated carrier In coherent phase modulation of digi 95 tal data, the recovered reference carrier is sometimes reversed in transmission by 180 '.
This would result in the waveform 16 of Fig 4 having peaks where there should be valleys, and vice versa However, since 10 ( both a peak and a valley are in an outer zone, it makes no difference if there is a phase reversal-the data detector and reconstructor will arrive at exactly the same result 105 An alternative system, also using digitallydifferentiated pulses, is shown in Fig 6 The same data waveform 16 (Fig 4) passes through the pair of slicers 26 and 27 The outputs of the slicers are the same as before, 110 and are shown in waveforms 21 A and 21 B (Fig 4) The first part of the data reconstructor of Fig 6 between the slicer outputs and the output of flip-flop 28 is used to reconstruct waveform 14 (Fig 4) When 115 the slicers indicate that the amplitude of waveform 16 is in the inner zone, the binary decision is to change the previous state, whatever it might have been When slicer 26 has a positive output, the decision is 120 always POSITIVE When slicer 27 has a negative output, the decision is always NEGATIVE These decisions are implemented by AND-gates 29, 30 and 31, and flip-flop 28 AND-gate 29 has an input con 125 nected to slicer 26 and an output connected to the SET input of flip-flop 28 AND-gate 31 has an input connected through an inhibitor to slicer 27 The inhibitor is required because the output of slicer 27, and 130 points 19 and 20 (Fig 5) and are shown in Fig 4 as waveforms 21 A and 21 B Each of these waveforms has two discrete amplitudes; one of these is a positive (or upper) amplitude-for example, amplitudes P and Q-and the other is a negative (or lower) amplitude-for example, amplitudes R and S When the amplitude of waveform 21 A is negative and the amplitude of waveform 21 B is positive, then the amplitude of waveform 16 lies in the inner zone Conversely, if either the amplitude of waveform 21 A is positive or the amplitude of waveform 21 B is negative, then the amplitude of waveform 16 falls in one of the outer zones.
The simplicity of the detection and reconstruction apparatus required is illustrated when waveform 16 is compared with the original data waveform 13 Whenever the amplitude of waveform 16 lies in the inner zone, there is a MARK in the corresponding portion of waveform 13; whenever the amplitude falls in the outer zone, there is a SPACE Therefore the logical circuit shown in Fig 5 must make only a single binary decision: is the amplitude within the inner zone? If, not, it must be in the outer zone.
The actual binary decision is made by two AND-gates 22 and 23, a flip-flop 24, and a pulse synchronizing means such as clock pulse generator 25 The AND-gates used and described herein are all of the type having an output only when all inputs are positive The first AND-gate 22 has an input connected through a conventional inhibitor (shown by its standard symbol on AND-gate 22) to slicer 17.
An inhibitor inverts the binary state of the signal, changing it from positive to negative, and vice versa AND-gate 22 has another input connected to slicer 18 and a third input connected to clock pulse generator 25 Its output is connected to the SET input of flip-flop 24 The other ANDgate 23 has an input connected through an inhibitor to the SET input of flip-flop 24.
It has another input connected to clock pulse generator 25 and an output connected O o to the RESET input of flip-flop 24.
Clock pulse generator 25 serves both to generate clock pulses at a rate equal to the bit rate of the transmitted data and to synchronize these pulses, so that they will be in phase with the data pulses The actual circuitry of the pulse generator and synchronizer is well known A more detailed description can be found in the Wier reference mentioned earlier.
When the slicers indicate that the amplitude of waveform 16 falls in an outer zone, AND-gate 22 will have no outnut, but ANDgate 23 does (because of the inhibitor) Flipflop 24 is then RESET, indicating a SPACE.
When the slicers indicate the amplitude of I 971,359 hence the input to AND-gate 31, is negative when the amplitude of waveform 16 is in the lower outer zone Since an output from AND-gate 31 is desired with this negative input, the input is first put through an inhi Litor The output of AND-gate 31 is connected to the RESET input of flip-flop 28.
AND ate 39 has an input connected through an inhibitor to slicer 26 and an input connected to slicer 27 The output of ANDgate 30 is connected to the COMPLEMENT input of flip-flop 28.
When the slicers determine that waveform 16 is in the inner zone, only AND-gate 30 will have an output, thereby causing flipflop 28 to change state by actuating its COMPLEMENT input When slicer 26 has a positive output, only AND-gate 29 has an output, and flip-flop 28 is SET When slicer 2 " 27 has a negative output, only AND-gate 31 has an output, and flip-flop 28 is RESET.
The waveform of the output of flip-flop 28 is identical to waveform 14 All of the ANDgates have inputs connected to a pulse syn25) chronizing means, such as a clock pulse generator.
The remaining part of the data reconstructor shown in Fig 6 between the output of flip-flop 28 and the output of the data reconstructor is used to reconvert the digitally differentiated waveform 14 (Fig 4) to the original data waveform 13 Flip-flop 32 provides a digital one-bit delay; the present bit appears at 33 and the previous bit at 34.
These two bits are compared in an EXCLUSIVE-OR circuit consisting of AND-gates and 36, and OR-gate 37 The binary decision based on the EXCLUSIVE-OR circuit is made by flip-flop 38 and AND-gate 39 The input of flip-flop 32 is connnected to the output of flip-flop 28 AND-gate 35 has one input connected through an inhibitor to the output of flip-flop 32 It has another input connected to the output of flip-flop 28 Its output is connected to OR-gate 37.
AND-gate 36 has an input connected to the output of flip-flop 32 and another input connected through an inhibitor to the output of flip-flop 28 Its output is also connected to the input of OR-gate 37 The output of OR-gate 37 is connected to the SET input of flip-flop 38 AND-gate 39 has an input connected through an inhibitor to the output of OR-gate 37 Its output is connected to the RESET input of flip-flop 38 All of the AND-gates have an input connected to a conventional clock pulse generator 40 to synchronize the pulses with the data source.
When flip-flop 38 and flip-flop 32 are both in the same binary state (the polarities of the present and previous pulses are the same), neither AND-gate 35 nor AND-gate 36 will have an output Therefore OR-gate 37 has no output This means AND-gate 39 will have an output (because the output of OR-gate 37 is connected to AND-gate 39 through an inhibitor), and Hlip-fop 38 will RESET This indicates a SPACE.
When the outputs of flip-flops 28 and 32 are different, then one or the other of AND 7 ( gates 35 and 36 will have an output and therefore so will OR-gate 37 In this case, flip-flop 38 is SET, indicating a MARK.
This system has a on -bit memory It has therefore a slightly higher error rate than 75 the system shown in Fig 5 which has nomemory However, when compared to a prior art quaternary system (having the same maximum bit speed), the system of this embodiment is far superior 80 Another embodiment of the data detector and reconstructor of the invention is shown in Fig 7 In this embodiment, the input data is not digitally differentiated before transmission Therefore the transmitted data is 85 waveform 41 shown in Fig 8 The received data from the transmission equipment is waveform 42 The amplitude zones are determined as explained above This data passes through slicers 43 and 44 (Fig 7) 90 and then appears as waveforms 45 A and B (Fig 8) When the slicers indicate the amplitude of waveform 42 lies in the inner zone, the decision is to chance the binary state, whatever it might have been (MARK 95 or SPACE) When slicer 43 has a positive output, the decision is MARK: when slicer 44 has a negative output, the decision is SPACE These decisions are implemented by the operation of gates 46, 47 and 48, and 100 flip-flop 49.
An input to AND-gate 46 is connected to slicer 43; its output is connected to the SET input of flip-flop 49 An input to ANDgate 48 is connected to slicer 44; its output 103 is connected to the RESET input of flipflop 49 AND-gate 47 has one input connected to slicer 44 and another input connected through an inhibitor to slicer 43; its output is connected to the COMPLEMENT 110 input of flip-flop 49 All three AND-gates have an input connected to a conventional clock pulse generator 50.
When the slicers indicate the amplitude of waveform 42 is in the inner zone, neither 115 AND-gate-46 nor AND-gate 48 has an output; therefore AND-gate 47 does have an output The state of flip-flop 49 is then changed When slicer 43 has a positive output, AND-gate 46 has an output, and the 120 flip-flop is SET, indicating MARK; when slicer 44 has a negative output, AND-gate 48 has an output, and the flip-flop is RESET, indicating SPACE.
This embodiment again has a memory 123 For that reason, it is also less desirable than the preferred embodiment, but again is superior to the prior-art quaternary system.
The substantial advantages provided by the apparatus of this invention, particularly 130 971,359 but the net result would be equivalent (except for the binary inversion), for the purposes of this invention Finally, waveform 65 18 ' is passed through a single slicer 191 to square the pulses, as shown by waveform 201 in Fig 9.
The simplicity of the detection and reconstruction apparatus using just one full-wave 70 rectifier and one slicer is immediately apparent Waveform 20 ' is identical to waveform 13 ', the transmitted waveform Whenever the amplitude line of waveform 201 is up, a MARK results; when it drops down, 75 a SPACE.
In the few applications where the amount of time jitter in waveform 20 ' is appreciable in comparison to the bit duration, the embodiment shown in Fig 11 may be used to 80 eliminate the jitter This embodiment uses a retiming circuit 21 ', which comprises two AND-gates 221 and 23 ', a flip-flop 241, and a pulse synchronizing means such as clock pulse generator 251 The AND-gates used 85 and described herein are all of the type having an output only when all inputs are positive The first AND-gate 22 ' has an input connected to slicer 19 ' AND-gate 221 has another input connected to clock pulse gen 90 erator 25 ' Its output is connected to the SET input of flip-flop 24 ' The other ANDgate 23 ' has an input connected through a conventional inhibitor to the SET input of flip-flop 24 ' An inhibitor inverts the bin 95 ary state of the signal, changing it from positive to negative, or vice versa The inhibitor is shown by its standard symbol on AND-gate 23 AND-gate 23 also has another input connected to clock pulse genera 10)0 tor 25 and an output connected to the RESET input of flip-flop 241.
In this embodiment, too, pulse generator 25 ' serves to generate clock pulses at a rate equal to the bit rate of the trans 105 mitted data, and to synchronize these pulses so that they will be in phase with the data pulses The actual circuitry of the pulse generator and synchronizer is well known.
A more detailed description may be found 110 in the Wier reference mentioned above.
Use of the retiming circuit eliminates the :slight jitter shown in waveform 20 ' Waveform 26 ' shows waveform 20 ' after it has emerged from the retiming circuit of the 115 embodiment illustrated in Fig 11 Even with the retiming circuit 21 ', the data detector and reconstructor of this embodiment requires no more equipment than a conventional binary data detector and recon 120 structor, yet it can unambiguously reconstruct data transmitted at a bit rate twice that possible with a conventional binary system.
The data detector and reconstructor shown 125 in Fig 10 or 11, too, has no memory bethe preferred embodiment shown in Fig 5, will be apparent from the following comparative example.
EXAMPLE.
) A system having the data detector and reconstructor shown in Fig 5 was compared with a conventional quaternary data communication system, both using an optimized FM transmission apparatus shown in Fig.
If 2 Both systems were designated for a parallel 16-channel application for a total of 2,560 bits per second over high-frequency radio voice channels All channels had identical bandwidths The tests were conducted with only a single channel The parameters of this channel were as follows (for both the system of this invention and the prior-art quaternary system):BIT SPEED 160 bits/second CENTER FREQUENCY 2125 cps SHIFT FREQUENCIES 2085 cps and 2165 cps CHANNEL BANDWIDTH 100 cps THERMAL NOISE flat A standard was established at an error rate of 10 ' This means that there will be an average of one error in 106 transmitted pulses The noise of each system was increased until this error rate was reached.
The normalized signal-to-noise ratio was then calculated This is the signal power for one bit per second capacity divided by receiver noise power in a one-cycle band (in decibels) With the system of the invention it was reached at a normalized signal-to-noise ratio of about 16 7 db; with the prior-art quaternary system, it was reached at about 20.5 db Thus about a 4 db decrease in noise sensitivity was achieved by the system of this invention.
In the modification illustrated in Figs 9, and 11 the digitally differentiated pulse is transmitted in one of the ways described earlier A data detector and reconstructor according to the-present modification of the invention is shown in Fig 10 The waveform 161 shown in Fig 9 is received from the transmission equipment This waveform has three amplitude zones: one inner zone and two outer zones, as shown The waveform is then passed through a full-wave rectifier 171 Such rectifiers are conventional and are usually made from a diode bridge circuit; further description here is not considered necessary for the, purposes of the present invention The waveform emerging from the rectifier is shown as waveform 18 ' in Fig 9 The top, half of waveform 161 was inverted by the rectifier to produce waveform 181 A reversed input to the rectifier would, of course, invert the bottom half of the waveform rather than the top half, 971,359 cause each binary decision is made strictly on the basis of a single pulse.
Figs 12 and 13 relate to an error detection apparatus for a new data system More specifically, this apparatus provides a way of detecting data transmission errors in a data transmission system of the type described above.
As will be recalled, the system described above supplies pulses representing binary data which are transmitted through a transmission channel The bit rate of transmission is up to about four times the frequency bandwidth limit of the transmission chan1.5 nel Because the data waveform is transmitted at such a high bit rate relative to the bandwidth of the transmission channel, it contains essential frequency components which the transmission channel is incapable of transmitting Consequently, the data waveform is not transmitted through the channel in its original form Nevertheless, there will be a received signal from which the original data can be reconstructed The received signal has three detectable amplitude zones, or levels These consist of two extreme levels, and one mean level between them Adjacent pulses, however, cannot be opposite extreme levels without an inter:30 vening mean level pulse The pattern of pulses in this new type of signal has been found to be quite unique The extreme level of a pulse which follows one or more successive pulses of the mean amplitude level ("mean level pulses") can be predicted on the basis of the number of such successive mean level pulses If that number is even, the next following extreme level pulse will be the same extreme level as that extreme level pulse immediately preceding the successive mean level pulses Contrariwise, if the number of successive mean level pulses is odd, the next following extreme level pulse will be the opposite extreme level from 4.5 the immediately preceding extreme level pulse.
The error detection system of this invention is quite different from conventional systems Normally certain extra pulses, called redundancies, are introduced along with the transmitted signal At the receiving end, these redundancies are checked for certain predetermined correspondence with the transmitted sienals If this correspondence fails to exist, errors have been made and are thus detected Such a system has certain inherent disadvantages First of all, additional equipment is required at the transmitting end of the system to introduce the hi 4) redundancies Similarly, extra apparatus is required at the receiver to remove them.
And finally, the requirement of transmitting extra bits which contain none of the data being transmitted necessarily reduces the number of data bits which can be transmitted in the system in any given time Thus data transmission is slowed.
Other prior art systems transmit a test pattern between transmission of data signals, designed to catch malfunctions in the 70 system This method, of course, also uses up valuable transmission time Furthermore, the check is made only between data transmission, and thus fails to detect any malfunctions developing during actual data 75 transmission.
This invention represents a departure from the prior art discussed above in that it takes advantage of certain properties of the data itself to check for errors No additional 80 bits, or redundancies, need be transmitted in the system of this invention Errors are detected during actual data transmission using the transmitted data itself for the check bits 85 Briefly, the apparatus of the invention uses a binary counter to check the number of successive mean level pulses to determine if that number is even or odd The output of this binary counter continuously predicts 90 whether the next following extreme level pulse, whenever it occurs, will be one extreme level or the other The apparatus also continuously monitors the transmitted extreme level pulses Each time one occurs, 95 it is compared with the prediction of the counter Where predicted and actual pulses fail to agree, an error is known to have occurred These errors may then be counted, or any other system used to indicate the de 100 gree of error recurrence Each time an error is detected, a preferred embodiment of the invention will reverse the state of the binary counter so that the counter will be in phase with subsequent transmitted data Then 105 the predicted extreme level and the actual extreme level will continue to agree until the next error occurs.
One type of error countina system uses a periodically reset step counter The step 11) counter counts the number of errors occurring between resettin-s If that number reaches a predetermined value, some kind of signal can be transmitted to indicate that the system is producing errors at a rate Greater 115 than should be tolerated Then corrective measures can be taken, or blocks of data can be retransmitted Usually a certain error rate is expected and tolerated Of course the actual number per unit time varies with 120 each system, and may also vary with the nature of the data being transmitted Therefore, it is preferable that either the period between resettings (usually set by a clock), or the number of errors tolerated (the num 125 ber which the step counter must count to have an output) be adjustable Such a system provides a variable error threshold level.
The apparatus of the invention can be 130 971,359 971,359 more easily understood from the following more detailed description, making reference to Figs 12 and 13.
It is most important in understanding the apparatus of the invention to first fully understand the construction of the transmitted waveform Such a waveform is shown in Fig 12 The three amplitude levels are clearly shown The upper extreme level is termed El, the lower extreme level E 2, and the mean level M Logically speaking, the mean level M is the level which will always occur when the amplitude is not one of the extreme levels Therefore, the level M can be expressed logically by the logic symbol El E 2, meaning "not El and not E 2 " It is this logical expression which is used for Mf in the apparatus of this invention, as will be explained later.
21) Looking at the waveform of Fig 12, note that the first two pulses 1 and 2 are pulses of extreme level El Pulses 3 and 4 are mean level, or M pulses There are two of them-an even number Therefore the prediction for the next extreme level pulse is that it will be the same extreme level as the last extreme level pulse immediately preceding the two successive mean level pulses.
That level was El Note that pulse 5 which immediately follows the two successive mean level pulses 3 and 4 is in fact extreme level El Thus, so far, the waveform is accurate, or as predicted As long as extreme level pulses continue to be received following pulse 5, they should remain in the same extreme level El Adjacent pulses cannot be of opposite extreme levels.
But the next following pulse 6 is a mean level pulse There is only one of them (an odd number) Therefore the next extreme level pulse is predicted to be the opposite from the previous extreme level pulse, which was an El pulse Sure enough, pulse 7 is an E 2 pulse-the opposite from the previous E 1 extreme level pulse So far, no errors.
Pulse 8 is again a single mean level pulse.
Pulse 9 should therefore be the opposite extreme level from the previous (E 2) extreme level pulse And it is an El pulse Pulses 10 and 11 follow pulse 9, remaining at the same El extreme level Remember that adjacent pulses can never be of opposite extreme levels There must be an intervening mean level pulse, -x Successive mean level pulses 12, 13, and 14 are three in number-an odd number.
The prediction then is that the next extreme level pulse will be the opposite from the last (which was El pulse 11) But pulse 15 is also an El pulse, the same as the last Hence an error has occurred This should be detected by the apparatus, as will be explained below.
Now referring to the apparatus shown schematically in Fig 13, slicers 2011 and 2111 are used to detect the amplitude level of the signal A slicer is a conventional amplifier switch which has an output signal when the input signal is of sufficient amplitude to turn the amplifier on Thus slicer 2011, used 70 to detect ET pulses, will have an El output when a positive El signal appears at its input Otherwise, its output will be El, indicating the absence of a positive El signal Similarly, slicer 2111 has an E 2 output 75 whenever a negative E 2 signal appears at its input Otherwise its output indicates the absence of an E 2 signal (E 2).
To obtain the M signal which indicates a mean level pulse the negative outputs of 80 slicers 20 " and 2111 are used The El and E 2 pulses are fed to a coincidence or ANDgate 2311 along with a clock pulse When the three pulses are coincident, meaning that a pulse was received which was neither an 85 El nor an E 2 pulse, the amplitude of the pulse must be M, or the mean level The output of AND-gate 231 " therefore indicates the receipt of a mean level, or M pulse The clock pulses fed into all the AND-gates of 90 the system serve to synchronize the slicer outputs with the transmitted data pulses.
These clock pulses are obtained from a conventional clock pulse generator, synchronized in bit rate and phase with the trans 95 mitter, as is well known in the art.
The M pulses are fed through OR-gate 24 "' into the complement input of a trigger flip-flop 25 " A trigger flip-flop is a conventional piece of logic circuitry which 100 changes state each time a pulse is received at its complement input Flip-flop 251 " has two outputs, one indicating each of its two states These have been designated x and x, or "not x" As will be immediately ex 105 plained, these outputs are used to predict which extreme level the extreme level pulse first following after a series of mean level pulses will be The x output of flip-flop 2511 is connected to AND-gate 26 ", where 110 it is checked for coincidence with the El output of slicer 20 " It must be remembered that flip-flop 25 " has a memory This means that even though no pulse is transmitted to its input, its present state will indicate the 115 state of the flip-flop which the previous pulse at its input placed it in Thus AND-gate 26 " compares the state of flip-flop 25 " as set by the last input pulse, with a pulse from slicer 20 " derived from an incoming 120 extreme level pulse During an incoming M level pulse (El E 2), slicer 20 " can have no El pulse, and slicer 21 " can have no E 2 pulse On the other hand, during receipt of an El pulse, while flip-flop 25 " is 125 in the x state, slicer 20 " 1 sends El pulse so that AND-gate 26 " will have an output.
Similarly, AND-gate 27 " has one input connected to the x output of flip-flop 25 " I O i and another input connected to the E 2 output slicer 2111 This AND-gate 27 " 1 checks for coincidence between an x state of flip-flop " and the receipt of an E 2 pulse from slicer 21 " The outputs of both AND-gates 26 " and 27 " are connected to an OR-gate 281 " When OR-gate 28 " has an output resulting from an output of either AND-gate 26 " or AND-gate 27 " an error has been detected, as follows.
Referring both to Figs 12 and 13, the first El pulse I is detected by slicer 20 ".
Although it makes no difference, let us assume that flip-flop 251 " was in state x.
The first pulse must always be disregarded in the error detection system This pulse is used to put the detection system in phase with the data The El pulse from slicer 201 " appears at AND-gate 26 " along with a clock pulse and the continuous pulse due to the x state of flip-flop 25 " Thus AND-gate 261 " and consequently OR-gate 281 have outputs Normally the output of OR-gate 281 " indicates an error But the first pulse is disregarded Note that the output of OR-gate 281 " is recycled to an input or OR-gate 241 " and on to the complement input of flipflop 25 " Thus flip-flop 25 " will change state because of this first El pulse Note further, however, that if the first pulse had been an E 2 pulse (with flip-flop 251 " still in the x state), AND-gates 26 " and 271 " would each have had only one input and thus no outputs, and hence OR-gate 28 " 1 would have neither an input pulse nor an output pulse.
Therefore the system would already have been in phase, and no change in the state of flip-flop 251 " would have either been necessary or transpired.
The next pulse 2 (Fig 12) is also an El pulse Flip-flop 25 " had been set to x by the last El pulse Therefore this next El pulse at AND-gate 26 " does not meet with an x state of flip-flop 251 ", AND-gate 261 " then has no output AND-gate 271 " also has no output (there was no E 2 pulse), and therefore OR-gate 28 " has no output ANDgate 231 ", of course, has no output during the receipt of extreme level pulses Flipflop 251 " thus remains unchanged.
Pulse 3 (Fig 12) is a mean level pulse.
Neither AND-gates 26 " or 271 " can have outputs because there are no El or E 2 pulses However, AND-gate 2311 will have an output, passed through OR-gate 24 " into the complement input of flip-flop 25 " The state of flip-flop 25 " 1 now changes back from x to x M level pulse 4 again changes the state of flip-flop 25 "-to x The fact that there were two successive M pulses (an even number) predicts that the next extreme level pulse should be the same as the last extreme level pulse, or El In faot, the next pulse-pulse 5 is El Since the El pulse from slicer 20 " coincides with an x 65 state of flip-flop 215 ", neither AIND-gates 261 " nor 27 " have outputs This shows there was no error.
This next pulse 6 is an M pulse Flip-flop 251 therefore changes state to state x A 70 single M pulse is an odd number of M pulses Therefore the next extreme level pulse must be the opposite from the previous extreme level pulse 5 (El), or E 2.
Pulse 7 is in fact E 2, coinciding with the 75 prediction of flip-flop 25 ", which is in state x Under these circumstances, again neither AND-gates 26 " nor 2711 have outputs because there has been no error.
M pulse 8 changes flip-flop 251 " to state 80 x Similarly, M pulses 12, 13, and 14 change flip-flop 25 " three times, ending in state x.
Pulse 15, as discussed earlier, is an erroneous pulse The odd number of M pulses preceding it predict that it should be the 85 opposite from the previous extreme level (El) pulse 11, or E 2 But in fact pulse 15 is El Flip-flop 25 " is in state x The El pulse therefore coincides with the x state of flip-flop 2511 and this produces an output 901 from AND-gate 2611 to indicate an error.
The error signal passes through OR-gate 281 " and OR-gate 24 " to change the state of flip-flop 251 " to x Now the error has been signaled (from OR-gate 28 ") and state 95 of flip-flop 2511 has been changed (through OR-gate 24 ") to again put it in phase with the data The next El pulse 16 will therefore check in as correct without indicating an error But one error will have been indi 10 t) cated at pulse 15 As long as the pulses are correct, OR-gate 28 " 1 will have no output signals, until the next error.
Normally, a data transmission system can tolerate a certain error level When this 105 tolerated level is exceeded, steps must be taken to correct the cause of the errors The tolerable error level may be ascertained by step counter 29 " Suppose that the system can tolerate up to 5 errors per second Step 110 counter 291 " then counts to five before having an output A clock pulse generator is connected to the reset input of step counter 29 " This clock pulse generator sends clock pulses to the step counter every second Such 115 pulses reset the counter to zero Thus, if less than five errors have occurred during the one second interval between resetting (the tolerable error level), step counter 291 " will have no output signal However, as 120 soon as the fifth error signal appears at the input of counter 291 " from the output of ORgate 281 " between two resettings, step counter 29 " will have an output This output indicates that the transmitted data has an error 1 '7level above the tolerable, or threshold level.
A warning signal may thus be flashed to the operator Or, if desired, the error signal can automatically cause the retransmission of 971,359 971,359 a previous block of data containing the errors The latter application is important in transmission of critical data, such as inventories, payrolls, and the like.
