An address converter for decoding a multi-bit binary address has a binary adder to provide a logic subtraction of binary bit information introduced by a plurality of manually settable switches from a predetermined number of most significant binary bits in an address signal, an address-decode circuit for receiving an output signal from the adder and the next order of magnitude of the binary bits in the address signal and a plurality of system subunits which receive an output signal from the addre...

A synchronizer for the address counter of an on-the-fly print wheel has two flip-flops complemented by paired photoelectric signals. One flip-flop responds to all character pads, or spaces, of the wheel and the other to all but one. When the two flip-flops fall out of step, a synchronizing signal is gated for setting the address counter and for also resynchronizing the two flip-flops, which then stay synchronized until the next unpaired signal.

An address converter for converting first addresses into second addresses which are fed to a memory of the data processing device, where the first addresses contain first and second address words and the second addresses contain third and fourth address words, the address words representing binary numbers, employs a comparator which is supplied with the first address word and a predetermined binary number and which is responsive thereto to emit a binary signal which assumes a first or a second b...

An address decoder comprises an OR circuit and a NOR circuit, the OR circuit having switching transistors to which decoder inputs and a chip enable signal are applied, a load transistory and a transistor for precharging a common precharge node by the complementary chip enable signal. The output of this OR circuit is applied to the NOR circuit with the complementary chip enable signal, the set-up time of the decoder or the NOR circuit being independent of the number of decoder inputs.

A memory addressing apparatus (1,20,90) is described comprising a circuit (5,26,96) responsive to a current external memory address on an input line (2,21,91) and a signal generated by an auxiliary memory circuit (8,29,93) for providing a current internal address for addressing an internal memory (15,19,101). For maximum program security, the above described components are all located in a single integrated circuit package.

An address decoder architecture capable of having a precharge signal for the word line coincident with the enabling of the decoder section to reduce the operating cycle. The word line latch is separate and distinct from the word line driver such that disablement of the word line driver during readdressing of the enabled decoder will not effect the portion of the cycle that the word line maintains its logic state.

An address buffer for a dynamic memory includes a flip-flop. The flip-flop is coupled at its one input/output terminal with both a first input circuit and a third input circuit connected in parallel with each other and at its other input/output terminal with a second input circuit. The second input circuit receives a reference voltage and is activated by an external address timing clock during a normal operation mode. The first input circuit is also activated by the external address timing clock...

A synchronizer for the address counter of an on-the-fly print wheel has two photoelectric cells, one of which generates pulses in response to all character pads, or spaces, of the wheel, and the other in response to all spaces but one. The unpaired pulse is used for setting the address counter.

An address comparator compares a write address value and a read address value for designating addresses in an elastic store circuit. More specifically, the count output of a write address counter (20) for counting a write clock signal is decoded by a write address decoder (30) and the count output of a read address counter (50) for counting a read clock signal is decoded by a read address decoder (40). The respective decoded outputs are classified into a plurality of groups so as to be supplied ...

An address generator which provides addresses for machine storage and software retrieval of computer status information. A counter is used to generate address signals in a descending order until it is disabled by a computer during alarm conditions. Under such conditions the counter provides a bias address for referencing the most recent status word. A gating circuit gates computer generated address signals to an adder circuit during the alarm conditions. The adder circuit adds the computer gener...