A method for decreasing entropy of a quantum system, for example nuclear spins. The quantum system comprising at least two subsystems, a first subsystem of elements with a first relaxation time (hereinafter--computation elements) and a second subsystem of elements with a second relaxation time (hereinafter--reset elements), the second relaxation time being shorter than the first relaxation time. The method comprises adiabatically decreasing the entropy of the computation elements in the system (...

A segmented algorithmic pattern generator engine producing a test signal pattern made of vectors divided into fully definable segments. The engine allows defining processing controls to allow offsets of individual vectors relative to one another and defining additional pattern control formats. Also provided are reducing the pattern format depths in defining counter dimensions within each segment. Single vectors or vector group sequences may be defined at any point as well. The system allows the ...

An algorithmic pattern generator produces an output data value during each cycle of a clock signal. The pattern generator includes an addressable instruction memory reading out an instruction during each clock signal cycle. A memory controller normally increments the instruction memory's address during each clock signal cycle, but may jump to another address N+1 clock signal cycles after receiving a CALL, RETURN, REPEAT or BRANCH command from an instruction processor. The instruction processor n...

The present invention is for an algorithmic method for compressing data. The data is compressed one cycle at a time and stores a data block each cycle. The method includes the steps of forming a storage array of binary bits. The array has a first plurality of columns, a second plurality of rows, a third plurality of right diagonals and a fourth plurality of left diagonals. In the preferred embodiment the array has 30 rows, 30 columns, 59 left diagonals and 59 right diagonals. The array also has ...

A processor architecture and instruction set is provided that is particularly well suited for cryptographic processing. A variety of techniques are employed to minimize the complexity of the design and to minimize the complexity of the interconnections within the device, thereby reducing the surface area required, and associated costs. A variety of techniques are also employed to ease the task of programming the processor for cryptographic processes, and to optimize the efficiency of instruction...

A digital to analog converter for converting an N-bit digital word into its analog representation including means for splitting the N bits into n sections of N/n bits each. For instance a 12-bit word is split into an odd section and an even section which are processed independently and in parallel. This results in two partial results, V.sub.i and V.sub.p, respectively, representative of the odd and even bit sections. The last step of the conversion is the action of the two partial results V.sub....

A segmented algorithmic pattern generator engine producing a test signal pattern made of vectors divided into fully definable segments. The engine allows defining processing controls to allow offsets of individual vectors relative to one another and defining additional pattern control formats. Also provided are reducing the pattern format depths in defining counter dimensions within each segment. Single vectors or vector group sequences may be defined at any point as well. The system allows the ...

A method of pipelining a disease specific diagnostic algorithm on an n-bit data word stored in a memory whereby the n-bit data word is divided into clinical tests describing ranges of normal values. Then, each of the clinical tests of the n-bit data word is read out from memory. Upon receiving a first of the results of the clinical tests, the result is compared with the normal value and the detection algorithm is computed based on the first result. This results in continuation with the next test...

According to the invention, a system for verifying a steganogram is disclosed. Included in the system are a first system, a second system, a steganogram, and a steganogram preparer. The first system is coupled to an access device by way of a public network. The second system coupled to the first system. The steganogram is comprised of random data and encrypted information, which is randomly dispersed throughout the steganogram. The steganogram preparer provides the steganogram to the access devi...

An algorithmic pattern generator for generating an output vector on each pulse of a clock signal includes a vector memory for storing a vector and an accompanying repeat number at each of several addresses. On each of N consecutive clock signal pulses, a repeat processor appends an instance of a vector read out of the vector memory to the pattern generator's output vector sequence. An instruction processor causes the instruction memory to read out instructions and responds to each instruction by...