A code converter circuit in a digital transmission system in which two mutually-synchronized digital signals are transmitted through a pair of transmission paths is disclosed. The transmission paths are characterized by the possibility of the terminal-to-terminal correspondence between input and output sides of the transmission paths being reversed. The code converter circuit includes an encoder on the input side of the transmission paths and a decoder on the output side of the transmission path...

The universal product code consisting of black bars and white spaces carrying information is discriminated by counting the occurrence period of electric signals corresponding to the guard pattern and averaging the count obtained thereby to provide a width information of the basic module, discriminating the first character by sampling the code in stop-start synchronization based on the width information, counting the occurrence period of electric signals corresponding to the (n-1)th character to ...

An extensible coded carrier provided with a binary code, consisting of a number of binary code elements mounted, for example, on a printed-circuit board. The code is capable of being extended to include an element which is analogue in principle, for example, a resistor. If desired, the analogue code element may be converted into a digital code element with the aid of a discriminator. The extended code may be used as an address to address a treatment programme.

A bit stream encoded in the Aiken or similar selfclocking code is converted into binary waveform with clocking by a sensor including two sensor elements spaced apart a critical distance. The elements read the bit stream independently. A logic circuit responsive to the outputs of the elements determines the data content of each bit as well as the timing of that bit. The apparatus permits code conversion of, for example, credit cards at point of sale (POS) apparatus independent of variations in th...

A bitstream encoded in the Aiken or similar self-clocking code is converted to a binary waveform with clocking by apparatus including two spaced apart sensing devices which read the bitstream, a memory circuit for storing the data content of the portion of the bitstream disposed between the sensing devices, and logic circuitry jointly responsive to the memory and sensing devices for determining the data content of the present bit. Timing information is extracted from the bitstream by another log...

A method and apparatus for code communication is disclosed in order to achieve band-width compression. Successive portions of information are derived and the next portion of information is predicted from at least one preceding portion, an error signal is then generated corresponding to the difference between the predicted portion and the next actual portion of information, whereafter the error signal is coded for transmission to a receiving device. The system is particularly described for coding...

A key reading system including a key having a plurality of rows of reading positions, each reading position cooperating with a reading position in each other row to form a set of reading positions. The reading system includes a clock line which senses all but one of the total number of code combinations of each set as a clock pulse, thus eliminating the need for a separate clock pulse row.

A code generator which has a plurality of selectable areas on an information plane of an information plate formed with a magnetostrictive material. At least one exciting winding is wound on the information plate at one end thereof for causing at least one magnetostrictive oscillation wave in the magnetostrictive material. A plurality of detecting windings are arranged on the information plate in parallel with the exciting winding to divide the information plane into a plurality of small areas. A...

A digital-to-analogue converter which uses a technique of two-level quantization in order to generate a pulse density code signal which yields the analogue signal when filtered. Standard digital logic adders and registers are used in the conversion of PCM signals to the pulse density code. The adders and registers are arranged as a feedback loop in which an approximation signal capable of either a "high" or a "low" level is compared repetitively with a PCM signal and the difference is accumulate...

This invention provides an improved magnetic core matrix code translator wherein each core in the decoder section thereof covers two digital possibilities rather than a "unique" digit representation. Moreover, each of the code wires running through the decoder cores is divided at the output thereof into anywhere from 2 to 32 branch lines which are then run through the cores of a coder stage to form 1-out-of-32 possibilities. These lines each terminate in a transistor switch operated by a control...