The computer system of this invention has, as the heart of the system, a simple processing unit for providing most data processing by the computer system under control of a read-only memory which contains only instructions and other data for the CPU. The system also includes a random access memory, a keyboard, a video terminal, and a port device in the form of a tape recorder/player. A master clock initiates timing used throughout the system. A multi-line data bus interconnects the CPU and the d...

The computer system of this invention has, a simple processing unit for providing most data processing by the computer system under control of a read-only memory which contains instructions and other data for the CPU. The system also includes a random access memory, a keyboard, a video terminal, and a port device in the form of a tape recorder/player. A master clock initiates timing used throughout the system. A multi-line data bus interconnects the CPU and the different memories of the system i...

A device including a housing having pulleys at opposite ends over which a plurality of belts extend being exposed along their substantial length on the top side. A slider having an opening extending transversely of said belts is movable over the belts. Chronological information is provided on the belts and may be viewed over a substantial period of time through the top of the housing or for one unit of time in the viewing opening in the slider. One of the belts is provided with projection measur...

A computer is disclosed wherein the machine language thereof is a particular formal system, i.e., the "calculus of lambda conversion." Such machine language is the language of the "well-formed" formulas of the aforementioned lambda calculus whereby the theoretical properties of the lambda calculus are implemented in the computer. Consequently, the computer is capable of computing all computable functions with time and space being the only limitations. The nerve center of the system is termed a t...

In normal digital computer operation each operation which is performed, normally requires a separate instruction. Time is required to obtain each instruction from storage and to decode each instruction. This invention comprises an improvement which provides means for performing several serial operations on several data words from different groups of words in response to a single instruction. This saves overall computer time, increases overall computer speed, and saves memory space.

According to this invention, a computer includes a register use information detecting unit for extracting pieces of information of registers, use of which is started and ended by executing instructions of a program, a register use information storing unit for storing information of a register whose value need be stored to execute an instruction in the program, a register use information referring unit for referring to register use information of the register use information storing unit, an inst...

Disclosed is a computer having a plurality of adapter cards which are insertable in adjacent bus segments, which are routed interleaved in the middle of a backplane and standard connectors are provided with connections alternating between the two bus segments. Both bus segments are connected to each other by a bridge circuit which includes at least one CPU adapter card. The invention is characterized by two bridge members each of which has an I/O unit and a CPU unit which are fixedly connected t...

A computer with a fixed casing accommodating at least one computer component and having an upward opening, a movable casing covering at least a part of the opening of the fixed casing and equipped with at least one computer component on its inner surface, a pair of hinges adjacent to opposite sides of the opening and rotatably supporting the movable casing, and a latch provided either the fixed casing or the movable casing, engaging and disengaging the movable casing to and from the fixed casing...

The invention relates to computer science, in particular, to a computer system comprising a processor, an input-output switch, an instruction loading switch, instruction memory, and a data access unit which uses the dataflow principle of computation. Performance is increased by decreasing the volume of associative memory by means of the introduction of the use of a fragment routine processor to process segments of the program which are better processed by von Neumann principles of computation.

A computer to computer data communication system for minimizing software protocol is disclosed wherein transmitted errors in data transmitted from one computer to another are detected when they occur by means of a bit-by-bit data echo transmission technique. True and inverted or complementary data are transmitted simultaneously serially over twisted pair lines for comparison, bit-by-bit by comparing each transmitted bit to the corresponding inverted bit to derive an error signal indicative of th...