A display system for displaying select dynamic process data of plant operations to an operator providing a display of only dynamic data having a predetermined difference between current and stored values.

An exception programming device in a reproduction machine capable of being programmed for a production run for producing a first plurality of copies of a document set having a common set of features and a second plurality of copies of the document set having selected features that are exceptions to the common set of features including single document input switches automatically providing selected exception features to the processor for a single identified document, the single document input swi...

A method for processing address translation exceptions occurring in a virtual memory system employing demand paging and having a plurality of registers and a real storage area, includes the steps of: (a) temporarily storing for each storage operation; (i) the effective storage address for the operation; (ii) exception control word information relative to the ones of the registers involved in the operation and the length and type of the operation; and (iii) any data to be stored during the operat...

A programmable processor includes a execution pipeline and an exception pipeline. The execution pipeline may be a multi-stage execution pipeline that processes instructions. The exception pipeline may be a multi-stage exception pipeline that propagates exceptions resulting from the execution of the instructions. The execution and exception pipelines may have the same number of stages and may operate on the same clock cycles. When an instruction passes from a stage of the execution pipeline to a ...

A method of analyzing train operational data recorded during each run of a train and transferred to a processing station. Operational and informational parameters are derived from the recorded operational data for each run. The operational and identification parameters and the corresponding operational data are stored as a standard database record for each run. The operational parameters are compared to selected exception values and the variance of the comparison are stored with the standard ope...

An exception processing system for use in conjunction with manufacturing facilities, and automated manufacturing cells in particular is provided. The exception processor is adapted to receive alarms from a cell controller indicating that an unplanned event or exception has occurred in cell operation. The exception processor implements an automated recovery procedure that responds to the alarm, corrects the exception, and returns the cell to normal operation. The exception processor also statisti...

A system and method for exception handling includes executing a first instruction. The first instruction then returns an exception. A program counter is used to determine the location of a second instruction. The second instruction includes a pointer to at least one exception handler.

A computer has a multi-stage execution pipeline and an instruction decoder. The instruction decoder is designed (a) to decode instructions of a complex instruction set for execution by the pipeline, the instruction set being architecturally exposed for execution by user-state programs stored in a main memory of the computer, the instruction set having variable-length instructions and many instructions having multiple side-effects and a potential to raise multiple exceptions, (b) for at least som...

A microprocessor system includes a core CPU for instruction execution and a coprocessor interconnected with said core CPU for system control and exception processing. The coprocessor includes a plurality of exception handling registers including an exception program counter having a restart location stored therein for use after an exception is serviced, a status register having operating mode identification and interrupt enabling bits, and a configuration and cache control register. Interrupt pr...

A circuit and method is provided for initiating an exception routine using exception information stored within architectured registers. Exception information is generated in response to a memory access exception caused by a speculative load instruction for loading a first register data from memory. The exception information, once generated, is stored within a first register. Thereafter, an instruction for operating on data stored in a second register is received and decoded. In response, the sec...