An interrupt system provides interrupt signals to devices to be interrupted by indicating the presence of interrupts in a random access memory associated with each of the devices to be interrupted. The address of the interrupt signal that is written is assigned to a respective one of a plurality of addresses, each of which is assigned to a respective one of a plurality of interrupting devices and is indicative of the priority of the interrupt. The controller associated with each of the devices t...

A circuit for tabling and processing interrupts on a priority basis including a separate table for each level of interrupt priority.

Disclosed herein is a method and apparatus for handling an asynchronous interrupt while emulating software so that the system is in a known state when the interrupt is handled. The method includes suspending the asynchronous interrupt so that it remains pending without interrupting software execution when it arrives, then synchronizing delivery of the interrupt to an instruction by issuing an exception. The instructions which trigger exceptions are inserted in the native code at locations corres...

The present invention relates to handling interrupts in a multiprocessor system. An interrupt controller can receive input from a variety of interrupt sources, such as peripheral components and peripheral interfaces. Interrupts and their associated characteristics are identified. In one example, interrupt characteristics can be compared with characteristics of other interrupts handled by processors in the multiprocessor system. Interrupt characteristics are used to select a processor to run a ro...

The disclosure relates to multiprocessor handling of plural queues of pending I/O interrupt requests (I/O IRs) in a main storage (MS) shared by plural central processors (CPs). An input/output processor (IOP) inserts I/O IR entries onto the queues in accordance with the type of interrupt. The entries in the queues are only removed by the CPs, after their selection by a system controller (SC) for execution of an interruption handling program. An I/O interrupt pending register in I/O interrupt con...

A method for managing interrupts in a microprocessor includes interrupts having a two-fold order of priority, i.e., a software priority and a hardware priority, wherein the microprocessor operates in two modes. During a first mode, the execution of an interrupt routine cannot be interrupted by the arrival of a new interrupt, even if it is a priority interrupt, unless this new interrupt is non-maskable. During a second mode, the execution of an interrupt routine is interrupted by the arrival of a...

A method and apparatus for conveying data over a packet-switching network. Data are received from a peripheral device for transmission via the network to a memory associated with a central processing unit (CPU), followed by an interrupt signal from the peripheral device associated with the data. One or more data packets containing the data are sent over the network to a host network interface serving the memory and the CPU, followed by an interrupt packet sent over the network to the host networ...

Method and system for managing interrupts originating from multiple sources is provided. The method includes assigning interrupt sources to a group; notifying an adapter of interrupt groups; identifying each interrupt group; writing a first interrupt to an interrupt module, where the interrupt occurs from a first source of the multiple sources; monitoring for a second interrupt; suspending the second interrupt until the first interrupt is processed, if the second interrupt is requested from the ...

Apparatus and methods are provided for transferring interrupts. One embodiment of a computing device includes a first processor, a memory in communication with the first processor, and computer executable instructions stored in memory and executable on the first processor. The computer executable instructions are provided to select an interrupt, that has been waiting to be processed, for transfer from the first processor, check a number of other processors to select a second processor that has a...

Systems, methods, and apparatus to retarget platform interrupts in a reconfigurable system. Some embodiments include identifying each processor of a multiprocessor system capable of processing Corrected Platform Error Interrupts, adding each processor capable of processing Corrected Platform Error Interrupts to a list of potential Corrected Platform Error Interrupt targets, and updating an interrupt table with a target processor for an interrupt, wherein the interrupt table is accessible by an i...