A high-density of semiconductor device is disclosed, which comprises a semiconductor substrate of a first conductivity type, first and second semiconductor regions of a second conductivity provided in the semiconductor substrate, the first and second semiconductor regions defining a channel region therebetween at the surface of the substrate, an insulator film disposed on the channel region, a conductive layer formed on the insulator film, means for producing depletion layers from the first and ...

A memory capable of reducing the memory cell size is provided. This memory includes a plurality of memory cells including diodes, a plurality of bit lines and a first conductive type first impurity region arranged to intersect with the bit lines for functioning as first electrodes of the diodes included in the memory cells and a word line. The first impurity region is divided every bit line group formed by a prescribed number of bit lines along a direction intersecting with the extensional direc...

A memory that includes a controller and a media including first information is provided. A first read/write mechanism is provided including an electron emitter configured to read the first information. The controller is configured to receive a first signal generated in response to the first information being read and generate a second signal configured to cause a position of the media to be adjusted relative to the electron field emitter in response to the first signal.

A memory capable of suppressing disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, and applies prescribed reverse voltages to at least non-selected first storage means connected to a non-selected word line substantially identical times respectively or substantially applies no voltage through a read operation and a rewrite operation.

A memory capable of suppressing disturbance is provided. This memory activates each of a selected word line and a bit line corresponding to unrewritten storage means while keeping potential difference therebetween at a level not more than a prescribed value and differentiates the length of a period for applying a voltage for rewriting to each of the selected word line and a bit line corresponding to rewritten storage means from the length of a transition period of the potential of at least eithe...

Memory system employed in a time compression scanner for monitoring telephone lines. Digital samples are written into the storage locations of a memory during one memory addressing period, and these samples are read out during the next memory addressing period, but in a different order from the order in which they were entered. As each sample is read out, it is replaced by a new sample which is to be read out during the subsequent memory addressing period. The memory address for writing in and r...

A memory capable of suppressing reduction of data determination accuracy is provided. This memory includes a memory cell connected to a bit line for holding data and a bipolar transistor whose base is connected to the bit line. In data reading, the memory reads the data by amplifying a current, corresponding to the data of the memory cell, appearing on the bit line with the bipolar transistor.

A memory includes an access control portion performing an internal access operation on the basis of an external access operation, a refresh control portion performing a refresh operation, a refresh division control portion dividing the refresh operation into a read operation and a rewrite operation and an address determination portion determining whether or not an address to be subjected to the refresh operation and an address to be subjected to the external access operation during the refresh o...

A memory capable of performing a refresh operation without increasing current consumption is provided. This memory comprises a plurality of memory cells storing data, a delay circuit outputting a first address signal corresponding to the memory cells received from outside for a normal access operation with a delay of a prescribed period, a refresh control circuit outputting a second address signal corresponding to any of the memory cells subjected to a refresh operation of the data and a switchi...

A memory capable of suppressing disturbance causing disappearance of data from a nonselected memory cell is provided. This memory applies a second voltage of polarity reverse to that of a first voltage applied to a nonselected memory cell in a read operation to at least the nonselected memory cell in addition to the read operation collectively performed on all memory cells connected to a selected word line.