A precharge circuit having improved equalizing function and suitable for a high-speed digital circuit is disclosed. The circuit comprises a pair of precharge nodes, an equalizer insulated gate field effect transistor connected between said nodes and means for operatively supplying a gate of the equalizer transistor with a voltager larger than a power supply voltage thereby to operate the equalizer transistor in a triode region.

Improved precharge circuit for a dynamic circuit having N, spaced apart, outputs; where N is an integer greater than 2. The conduction path of a precharge transistor is connected between each pair of outputs, whereby (N-1) precharge transistors are connected end-to-end between the N output points. At least one additional precharge transistor is connected between one of the N outputs and a precharge potential point. A common conductor interconnects the control electrodes of all the precharge tran...

A precharge circuit is provided with a step-up node circuit including a capacitor for delivering a drive voltage at a predetermined level to a load, and for raising the voltage level of the drive voltage so that it becomes equal to a value greater than the predetermined level by a specific value. This precharge circuit at least comprises a main P-channel MOS transistor for delivering the drive voltage at the predetermined level to the load through the step-up node circuit when a step-up input si...

A precharge circuit prevents voltage dropping of a local input/output line in a semiconductor memory apparatus. The precharge circuit includes at least one pair of pull-up and pull-down precharge circuits. When a local input/output line precharge signal is enabled, a precharge voltage to be applied to each of the precharge circuits is supplied to a local input/output line and a local input/output line-bar. The pull-up precharge circuit has P-type MOS transistors, and the pull-down precharge circ...

An architecture and method for fast precharge of bitlines in a densely packed, dynamic content addressable memory is disclosed. The dynamic content addressable memory cells are arranged according to an open bitline architecture to obtain high packing density. The bitlines are precharged through equalization between every two adjacent open bitline pairs. More specifically, a bitline and its adjacent neighbouring bitline on the same side of the bitline sense amplifiers are equalized at several loc...

An architecture and method for fast precharge of bitlines in a densely packed, dynamic content addressable memory is disclosed. The dynamic content addressable memory cells are arranged according to an open bitline architecture to obtain high packing density. The bitlines are precharged through equalization between every two adjacent open bitline pairs. More specifically, a bitline and its adjacent neighboring bitline on the same side of the bitline sense amplifiers are equalized at several loca...

Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a processor requests an external memory controller to close a storage location of a memory associated with a first memory transaction based upon a relationship between the first memory transaction and a second memory transaction.

A precharge circuit that initializes an electronic filter to a middle voltage level of an operational voltage includes a filter isolation device, a filter communication device, and an initializing device. The filter isolation device isolates the electronic filter from electronic circuits connected to an input and an output of the electronic filter to segregate the electronic filter from the electronic circuits connected to the input and the output of the electronic filter during a precharge time...

An automatic precharge gas pressure adjuster for a hydraulic desurger for automatically adjusting the precharge gas pressure in response to operating changes in system fluid pressure thereby maintaining a constant volume of precharge gas in the desurger. The adjusting unit comprises a cylinder divided into two chambers by a spring-biased differential-area piston. The system fluid pressure communicates with the chamber facing the first or largest area piston face while precharge gas communicates ...

In MOS circuitry, such as a dynamic MOS random access memory, precharge circuitry, consisting of six p-channel MOS transistors and a seventh p-channel MOS transistor connected as a capacitor, facilitates a two step charging process that initially lowers the potential of a first circuit node from a high potential to a value approximately one threshold voltage above an available low level power supply potential and then further lowers the potential of the circuit node to a value below that of the ...