A snap-action switch comprising a snap member carrying a first electrical contact connected to a first electrical contact connected to a first electrical terminal which can be snapped through an unstable center position by pressure applied through the contact, a stationary second electrical contact connected to a second electrical terminal and engaged by the first contact when the snap member is in a first stable position, a wedging member mounted for sliding movement along the stationary second...

In a data transmission system, a switching network in a connection node (VK) includes switch groups (SCH) for switching channels, which are each assigned to one or more time slots within the framework of a multiplex time signal, e.g. virtual containers of a STM-1 frame according to CCITT recommendations G707 to G.709. Each switch group (SCH) is modular and linked to one another, and contains a memory (DS) with several independently readable memory outputs (SA1 to SA4), through which the storage ...

The invention relates to a switching network for a switching system in which cells are transmitted in accordance with a time division multiplex method and the through-connection is effected by means of the routing information contained in the header of the cells. The blocks arriving at the switching node are temporarily stored in a queuing buffer until a free frame is available. A switching network should be configured in such a manner that the number of buffer spaces can become as small as poss...

A switching regulator includes an inrush current protective resistor and a starter circuit for a pulse width modulator consisting of a starting resistor and a capacitor. At initial starting mode, the inrush current protective resistor is connected to the starter circuit, and after starting both of the inrush current protective resistor and starting resistor are disconnected so as to reduce power dissipation or consumption thereby. At the same time, a DC voltage source for the pulse width modulat...

A switching regulator includes a chopper circuit and a DC-DC converter. A switching signal for use with the chopper circuit is derived from an inverter portion of the DC-DC converter so as not to use an external pulse oscillator. A DC voltage feedback circuit is provided from the output of the DC-DC converter to the chopper circuit so as to stabilize the DC output signal of the DC-DC converter. Alternatively, the DC voltage feedback is provided from an output of the chopper circuit.

A switching arrangement comprises a spring-loaded clockwork movement and a switch to control a device, the movement of the spring itself, as it is tensioned or becomes substantially de-tensioned, being utilized to operate the switch.

A switching circuit including a flip-flop which receives a switching signal that sets the flip-flop and which receives a reset signal which resets the flip-flop. A latching circuit, responsive to a clock signal, is connected to receive an output signal of the flip-flop for developing a latching circuit output signal corresponding to the output signal of the flip-flop at a time the clock signal is applied thereto. A reset signal and a clock signal developed repetitively and out of phase are respe...

First through fourth NPN switching transistors having bases receptive of first through fourth control signals, respectively, are connected in cascode between a first terminal, for receiving an operating voltage +E.sub.1, and a second terminal for receiving a source of reference potential. The common connection between the second and third transistors is connected to an output terminal. A first diode is connected between a third terminal for receiving a clamping voltage +E.sub.2 and the common co...

A switching regulator includes a DC voltage source having a pair of DC output terminals, a switching transformer having first and second primary windings connected in series, a magnetic core and a secondary winding, a first switching transistor connected in series between the pair of DC output terminals through the first primary winding, a second switching transistor connected in series between the pair of DC output terminals through the first and second primary windings, a rectifier circuit con...

Buffer means are included in the input circuit in a switching comparator. The unavoidable shunt capacitance at the comparison node is thereby isolated from the input terminal. This substantially reduces the comparator d-c input loading to improve comparison accuracy particularly with sources having appreciable internal resistance.