The object of the present invention is to provide a synchro-spring to be used in a synchronizing mechanism having insert-shifting keys. Said synchro-spring is characterized by shaping convex forms in the portions which come into contact with said insert-shifting keys, and when this synchronizing mechanism is used for an automobile transmission, an enough capacity of the synchronizer ring can be ensured without increasing the size of the synchronizing mechanism, and smooth gear shifting is attain...

A synchronizing circuit is disclosed which enables a desired phenomena to occur, such as the discharge of a flash illuminating means at a precise point along the path of travel of an article irrespective of the speed of the article in that path. The circuit utilizes two spaced sensors upstream of the precise point. The sensors are operable to detect the passage of the article and each sensor is connected to respective counter. When sensor detects the passage of the article it starts its respecti...

1. In a communication system utilizing at least two independent binary coded pulse signal sequences, means for achieving and holding time synchronism between said two sequences which comprises the combination of pulse recurrence frequency searching means for controlling the pulse recurrence frequency of one of said signals relative to the other to bring said signal into synchronism with the other, and phase locking means including a periodic phase checking circuit and a phase variation correctin...

A synchronizing device, particularly for automobile gear units with an axially slidable sleeve. Rams pass axially through the sleeve and there are means in the sleeve for limiting the shifting power. There is a transversely directed hole in the sleeve with pressure pieces at each end for contacting the rams, and a spring in the hole urges the pressure pieces outwardly to limit the ram movement. There can be several transverse holes arranged in a polygon about the sleeve.

A synchronizing circuit provides a plurality of signal transmission paths having different delay times in the line for transmitting signals. A pilot signal circuit has a pilot signal generator circuit which operates on the sending side, and a pilot signal is sent via one of the paths having a different delay time to a plurality of latch circuits on the receiving side. The output of each of the latch circuits is compared by a predicting circuit, so as to predict the phase difference between the c...

A synchronizing ring (1) adapted for use in a gear clutch where the ring includes an annular body (2) formed of a chip-free material, such as a metallic body of forged or sintered material or a plastic, and having a generally conical friction surface (6) with a fibrous friction lining (3) cemented thereto. The ring has one or more generally axially extending grooves (5) formed in the friction material to provide for draining of oil during operation of the ring.

In a synchronizing circuit, such as a DPLL (Digital Phase-Locked Loop), adapted to be synchronized in accordance with clock signals of an external clock, a programmable timer in the circuit is forcedly reset in synchronism with the edge of an external clock signal pulse at the time of the clock signal's initial state in accordance with a clock detection circuit. Subsequently, baud timing of the external clock signals is detected by making use of internal clock signals produced by the circuit. Sy...

A synchronizing system is provided for reliably passing data across a boundary between two independent, non-correlated clocks, referred to as the receiving and transmitting clocks. The system reduces occurrence of errors due to asynchronous samplings to an arbitrarily low level based on metastable operation. The system is organized as a two port memory with unit distance code addressing the memory cells. It performs a handshake between the two non-correlated clock systems to allow for any ratio ...

A circuit for synchronizing data pulses, comprises a D-type flip-flop and a set-reset type flip-flop. The D-type flip-flop is enabled by a system clock pulse train wherein the D-type flip flop conducts to product an output at a time controlled by the system clock pulse train if a data pulse is present, thereby synchronizing the data pulse with the system clock. The set-reset flip-flop is enabled by a second clock pulse train which lags after the system clock pulse train. The lag period is long e...

A phase locked loop circuit regenerates a synchronizing signal. A first counter counts adjustable and fixed time intervals. A flip/flop generates synchronizing pulses having periods defined by sets of the adjustable and fixed time intervals. A second counter successively measures phase differences between synchronizing pulses and input pulses related to a synchronizing component in a video signal. The phase differences are measured between the ends of the adjustable time intervals in the synchro...