File operations on files in a peripheral system are controlled by an intelligent controller with a file processor. The files are accessed as if the intelligent controller were an addressable virtual storage space. This is accomplished first by communicating controller commands for the intelligent controller through read/write commands addressed to a Command Region of a virtual storage device. The controller commands set up a Mapped Data Region in the virtual storage device for use in controlling...

A semiconductor memory comprises four arrays (10), (12), (14) and (16) disposed on a single semiconductor chip. Each of the arrays has a serial shift register (86) associated therewith. Data is transferred from the bit lines of the associated array through a transfer gate (90) for storage in the shift register (86). A tap latch (88) is provided on the output of each of the shift bits in the shift register (86) for determining the output therefrom. The tap latch (88) stores a tap decode signal wh...

A semiconductor memory is comprised of four arrays (10), (12), (14) and (16) that have the memory elements therein arranged in accordance with pixel positions on a display. The memory arrays have associated shift registers (34), (36), (38) and (40) which have data loaded in parallel and output in a serial format to the display. Each of the shift registers can be connected in a circulating fashion or a shift register of adjacent arrays can be cascaded. Switches (56), (58), (60) and (62) are provi...

A semiconductor memory circuit includes memory arrays (10), (12), (14) and (16). Each of the memory arrays has associated therewith shift registers (34), (36), (38) and (40). Transfer gates (54) are disposed between the memory arrays and the associated shift registers. A control circuit (69) is provided for receiving an external transfer signal and transferring the data between the arrays and the associated shift registers. The shift registers are clocked in response to receiving an external shi...

A flash memory control apparatus and method which enables updating of data at high speed. The flash memory control apparatus includes a flash memory having a memory region which is divided into a plurality of sectors each including a logical address portion for storing a logical address of the sector, an erasure managing portion for storing information which indicates at least whether or not the sector may be erased, and a data part for storing data; and a control device, coupled to the flash me...

A flash memory control apparatus and method which enables updating of data at high speed. The flash memory control apparatus includes a flash memory having a memory region which is divided into a plurality of sectors each including a logical address portion for storing a logical address of the sector, an erasure managing portion for storing information which indicates at least whether or not the sector may be erased, and a data part for storing data; and a control device, coupled to the flash me...

One embodiment of the present invention provides a memory system that allows more than one cycle of memory latency for accesses to a synchronously accessed memory. In this embodiment, the memory system includes a memory with a clocked interface and a corresponding clock input. It also includes an output register for storing data outputted from the memory during a read operation. The output register and the memory are coupled together by a data path, for transferring data between the memory and t...

A method for discovering frequently accessed subtrees, performed by an electronic apparatus, comprises the following steps. A request is received from a source. A global prefix tree (GPT) comprising multiple traversal paths is acquired, each traversal path representing one of a plurality of frequently accessed subtrees. A response comprising the GPT is transmitted to the source, thereby enabling the source to discover the frequently accessed subtrees based on the GPT. The GPT is generated in res...

A system and method for analyzing data accesses to determine data accessing patterns is provided. Data address accesses are traced and transformed into Whole Program Data Accesses (WPDAs). WPDAs may then be used to discover higher-level data abstractions, such as hot data blocks. Hot data blocks provide information related to sequences of data addresses that are repeatedly accessed together. Hot data blocks may then be used to improve program performance.

A system and method for analyzing data accesses to determine data accessing patterns is provided. Data address accesses are traced and transformed into Whole Program Data Accesses (WPDAs). WPDAs may then be used to discover higher-level data abstractions, such as hot data blocks. Hot data blocks provide information related to sequences of data addresses that are repeatedly accessed together. Hot data blocks may then be used to improve program performance.