Composite mutually exclusive field-accessed circuit elements common to a plurality of bubble paths. A channel composed of mutually exclusive circuit elements is linked to an adjacent parallel channel of mutually exclusive circuit elements by means of circuit element portions common to both channels. The interconnected channels are operated mutually exclusively by means of corresponding pulsed field sequences. Transfer between the linked channels is via the common circuit element portion. Several...

A memory device is provided with first and second memories. Two groups of data are loaded into the first and second memories, through a data buffer register. The same address information is applied to the first and second memories and the information is read out from the first and second memories. The two groups of the data read out in parallel are applied to a data multiplexer which in turn converts the parallel information into the serial one.

Disclosed is a method, system, and program for caching data. Data from a device, such as a volatile memory device or non-volatile storage device, is maintained in entries in a cache. For each entry in cache, a variable indicates both a time when the cache entry was last accessed and a frequency of accesses to the cache entry. The variable is used in determining which entry to denote from cache to make room for subsequent entries.

Page management mechanisms provide candidates for page stealing and prefetching from a main storage data cache of shared data when the jobs sharing the data are accessing it in a sequential manner. Pages are stolen behind the first reader in the cache, and thereafter at locations least likely to be soon re-referenced by trailing readers. A "clustering" of readers may be promoted to reduce I/O contention. Prefetching is carried out so that the pages most likely to be soon referenced by one of the...

An integrated circuit with a serial data port includes a counter for counting clock pulses and generating a binary signal, a decoder for converting the binary signal to a load signal to access an appropriately sized register, a serial-in, parallel-out shift register for receiving serial data and outputting the data in parallel, and a plurality of registers. The registers receive the load signal from the decoder and have a multi-bit data input for receiving the parallel data from the shift regist...

In a semiconductor memory having a column-direction serial access function, two systems of circuits for selecting and fetching data are provided. A circuit operation is alternately performed such that one system is set up while the other system is accessed, thereby reducing a cycle time for a data selecting/fetching operation.

The semiconductor memory device contains a plurality of memory cells, a row decoder for selectively actuating memory cells according to the selected one of the row and column address signals, and bit lines set to a potential dependent on the data in the memory cell actuated. Particularly, this memory device has latching circuits for latching the potentials on the bit lines, and a timing controller for causing the latching circuits to keep the latched potentials for a predetermined period after t...

A method and apparatus for handling an accessed bit in a page table entry is provided. When a page table entry is not present in a translation lookaside buffer (TLB), an electrical circuit causes a TLB miss exception and branching to a first software exception handler. The first software exception handler fetches the page table entry from main memory. The first software exception handler places the page table entry in the TLB. An electrical circuit determines whether an accessed bit of the page ...

The present invention relates to a high-speed high-capacity Local Area Network (LAN) wherein each user, of a separate group of one or more of the network users, communicates cordlessly, using radio frequencies or infrared, with an assigned Regional Bus Interface Unit (RBIU) located in the proximity of the group. Each RBIU of the network interfaces with a high-speed serial or lower speed parallel bus of an open-ring network for purposes of transmitting information signals while receiving informat...

A prefetching mechanism for a system having a cache has, in addition to the normal cache directory, a two-level shadow directory. When an information block is accessed, a parent identifier derived from the block address is stored in a first level of the shadow directory. The address of a subsequently accessed block is stored in the second level of the shadow directory, in a position associated with the first-level position of the respective parent identifier. With each access to an information b...