An image processing system according to the present invention is provided with a first switch control section configured to select clocks in accordance with an image processing mode, from among a plurality of clocks a first clock generating section generates for operating an image processing section, a storage section used for image processing, and a second clock generating section which enables an operation to be performed based on clocks faster than those used in the image processing mode, in ...

Systems and techniques to detach and reattach tabs presenting accessed objects in a multi-tab interface for a software application. In general, in one implementation, the system includes a windowed environment, and an application using the windowed environment and employing an application navigation structure. The application navigation structure includes a multi-tab user interface to objects handled by the application. The multi-tab user interface includes a tab-strip presenting opened objects ...

A control store for a microprocessor is divided into two segments with one segment of the control store located on the microprocessor chip and the other segment of the control store located on a separate chip. In multiprocessor applications, a number of the microprocessors share the control store segment on the separate chip. Each control store word includes a field containing a prediction of the address for the next control store word needed by the microprocessor. The predicted address is used ...

A computing system and method employing a processor device for generating real addresses associated with memory locations of a real memory system for reading and writing of data thereto, the system comprising: a plurality of memory blocks in the real memory system for storing data, a physical memory storage for storing the pages of data comprising one or more real memory blocks, each real memory block partitioned into one or more sectors, each comprising contiguous bytes of physical memory; a tr...

A table, such as a database table can be partitioned into blocks that are conveniently sized for storage and retrieval. The amount of storage space required and the speed of storing and retrieving blocks is proportional to the size of the blocks. Compressing the blocks leads to less required space and more speed. The columns in a table, and therefore the rows in a transposed block, tend to contain similar data. Compression algorithms can work more efficiently when sequential data items are simil...

Apparatus, methods and computer programs provided for metering and accounting in a commercial e-services infrastructure address the requirement for handling composite services in which higher-level services are built using simpler underlying services, each of which may be autonomously owned and operated. Metering records for each service underlying a composite service are correlated by a process associated with the composite service, and then sent to an accounting service where they can be aggre...

A database warehouse includes a database having data arranged in data tables, e.g., fact tables and reference tables. A warehouse database hub interface is connected to the database. The warehouse database hub interface presents to a user a schema of the data in the database warehouse. The schema consists of virtual tables. Arrangement of the data in the virtual tables is different than arrangement of data in the fact tables and the reference tables. A user generates queries based on the schema ...

A method for moving open files on a computer system is disclosed. According to one aspect of the invention, an open file may be accessed by a user while being moved. To ensure accuracy, if data is to be written to an open file while it is being moved, the data is written to both the old and new locations.

In a semiconductor memory, a plurality of semiconductor memory modules are connected through a common clock signal line and one or more other signal lines to an accessing circuit. The accessing circuit has a timing information storage unit for storing predetermined access timing information associated with the respective semiconductor memory modules, and a timing varying unit for varying a data receiving timing at a transfer destination in compliance with a semiconductor memory module to be acce...

A memory cache interface (12) serially accesses each way in an M-way set asociative memory cache (11) when it performs a read operation. The memory cache returns a data quantum and a tag corresponding to each presented input. The memory cache interface presents a portion of a main memory address and a new value of a way signal to the memory cache until it finds a match between the output tag and the remainder of the main memory address. The memory cache interface allows set-associative caches to...