A memory array includes row conductors which have to be charged to a first level prior to each read-out cycle. During a read-out cycle the row conductors may or may not be discharged to a second level depending on whether a "1" or a "0" is stored at selected bit locations. The memory array also includes "dummy" row conductors which are discharged to the second level each time the contents of the array are read out. Means are provided for charging the row conductors including the "dummy" row cond...

An integrated circuit memory array having a plurality of memory cells including two cross-coupled transistors of one conductivity type, load transistors of the other conductivity type, and a bit line, connected to the base region of one of the cross-coupled transistors through a bit line transistor. The array features a common node, directly interconnecting all of the base regions of the load transistors and the emitter regions of the cross-coupled transistors, for each of the memory cells; and ...

A flash array which is provided with a transparent electrically conductive layer which serves to prevent spontaneous ignition of a flash lamp in the device. The flash array is provided with high voltage combustion flash lamps and the transparent electrically conductive layer consisting of conductive indium oxide which is applied to the inner side of a transparent cover of the array. The resistance per square of that layer is smaller than 100 kOhm, so that for these lamps -- which are, for exampl...

An improved seismic array is disclosed having a plurality of seismic detector connection points with a seismic detector at each seismic detector connection point. The output of each seismic detector in the array is weighted by providing first resistive weighting at each seismic detector connection point. The weighted output of all detectors in the array is provided to a first end of the array over a single pair of wires. An amplifier is additionally provided for connection to the pair of wires a...

A line scanning apparatus employing a multiplicity of linear arrays, the linear extent of which is less than the length of the scan line. To permit an entire line to be covered, the arrays are offset from one another in the direction of scan with adjoining array ends overlapped. To correct for the misalignment and redundancy introduced, the image data from the arrays is buffered until a line is completed when readout is initiated. During readout, cross over from one array to the next is effected...

A flash array has at least two combustion flash lamps and an indicator which indicates whether a lamp has or has not flashed. The indicator consists mainly of a melting strip which is constructed as a radiation-sensitive switch contact and which is part of the electric circuit of the flash array.

This describes a bipolar dynamic RAM cell array in which there is provided a plurality of capacitive storage data cells each being coupled to a respective capacitively loaded bit line and to one another through a common word line. A supply means is coupled to the word line for biasing each cell of the array with respect to its respective bit line to cause the bit line capacitance to set the conductive state of each cell so as to set the respective capacitive storage means of each cell to a selec...

In an Array Processor, a buffering unit including a FIFO buffer and serial-to-parallel converter, is interposed between a control processor and the remainder of the Array Processing circuitry so as to permit the utilization of a vertical instruction set for generating addresses and function numbers which are then serially coupled from the control processor to the buffering unit.

An array processor is described consisting of a plurality of modules connected together in rows and columns. Each module has at least one special terminal which, as well as providing a connection for transfer of data between adjacent modules, also provides an output which is combined with similar signals from the other modules in the same row, to form a row response signal. Alternate modules in each row are rotated by 180.degree. with respect to each other, so that the special terminals on adjac...

An array processor consisting of integrated circuit chips connected in a rectangular array. The number of terminals on each chip necessary for these interconnections is reduced by arranging for certain terminals to be connected to branched paths, so that those terminals are shared between different connections. Special gating is provided to ensure that signals are routed correctly over these shared connections.