A buffer circuit comprises a flip-flop which is receives an external input via a first input circuit and a reference voltage via a second input circuit. Internal complementary outputs are then produced via an output circuit. The flip-flop cooperates with at least one level setting device by way of a second input circuit. The level setting device functions to produce a voltage level to deactivate the second input circuit during activation of the flip-flop.

An address buffer for a dynamic memory includes a flip-flop. The flip-flop is coupled at its one input/output terminal with both a first input circuit and a third input circuit connected in parallel with each other and at its other input/output terminal with a second input circuit. The second input circuit receives a reference voltage and is activated by an external address timing clock during a normal operation mode. The first input circuit is also activated by the external address timing clock...

An input buffer circuit for a memory uses two transistors interposed between a push-pull pair of transistors to control the enabling of the buffer in response to a chip write signal generated from a logical combination of chip select and write enable signals. A plurality of inverters which provide complementary signals to the push-pull transistors are disabled and prevented from using current by an interrupt transistor until the interrupt transistor receives the chip write signal.

A plate is attached to a rail which moves vertically in a housing. The housing includes a brake which rubs on one side of the rail; on the other side, there is a roller. A leaf spring is positioned between the housing and the roller. When the rail moves vertically in one direction, the roller is pushed progressively harder against the rail. This squeezes the rail against the brake, creating a braking force on the rail that increases, to maximum, in relation to distance the rail moves. This arran...

An input buffer circuit for translating TTL level inputs to CMOS levels and which constitutes a part of a monolithic semiconductor device is provided. An input inverter stage has the source of its load transistor connected via a bipolar transistor to a first voltage level. When a second voltage level at which the monolithic semiconductor device is intended to operate exceeds the first voltage level, an MOS transistor coupled in parallel with the bipolar transistor bypasses the bipolar transistor...

A buffer amplifier input circuit includes both field-effect and bipolar transistors arranged in conjunction with an operational amplifier to provide very stable operation over a wide frequency range.

A memory buffer is provided between a receiving system and a digital computer to provide an indication of the number of times pulses from the same source have been received in a predetermined interval of time upon interrogation of the memory buffer by the digital computer while such memory buffer continues to function without interruption during the interrogation process so that information from pulses received during such interrogation by the digital computer is retained.

A buffer amplifier suitable for use as an input amplifier for an oscilloscope comprises a hybrid FET-bipolar transistor source follower input stage and a complementary emitter follower output stage. Both the input and output stages include bootstraps to eliminate thermal transient response aberrations, to increase input impedance, and to maintain standing current in the output stage. Other attributes include a very short response time for high bandwidth operation, and high linearity.

A buffer circuit operable with high speed is disclosed. The circuit comprises an input node, an amplifying means having an input coupled to the input node, a first power source, a second power source, a first transistor coupled between the first potential source and the input node, a second transistor coupled between the input node and the second power source, and means responsive to the output of the amplifying means for respectively providing a first signal and a second signal complementary to...

The buffer circuit is provided with a high sensitivity balanced type flip-flop circuit and a capacative coupling provided by MOS capacitance, and a load drive circuit utilizes bootstrap effect, thus producing complementary signals having a MOS level from a TTL address input signal.