An input buffer having a differential amplifier 3 includes a protection circuit 4 located between an input terminal 1 and the differential amplifier. The protection circuit serves to protect a MOS transistor 5 constituting the differential amplifier when a high voltage is applied to the input terminal of the input buffer. The protection circuit is an N-channel type MOS transistor with a drain electrode connected to the input terminal, a source electrode connected to a gate terminal of the MOS tr...

The buffer device (10) has a body (11) which can be fitted in a rail (4), a damping element (12) for cushioning, and a retaining spring (13) for retaining a running mechanism (6) which is guided in the rail (4) and is provided for carrying and guiding slidable wing elements (2). The at least approximately U-profile-shaped body (11) of the buffer device (10), which body is punched and bent from a metal element, has a first and a second wing (14; 18), which wings are connected to each other by a c...

A tristate buffers includes a logic circuit which outputs a high-level signal. The output signal is fed to gates of 1st and 2nd P-channel MOS transistors (TRs). A 3rd PMOS TR has a gate connected to a drain of the 2nd PMOS TR, and a drain connected to a drain of the 1st PMOS TR. A 4th PMOS TR has a gate connected to the drain of the 1st PMOS TR, and a drain connected to the drain of the 2nd PMOS TR. A 1st NMOS TR and a 2nd NMOS TR have their drains connected respectively to the drains of the 1st...

A microwave buffer for use between transmitter modules and an impedance combiner. The buffer is comprised of a plurality of input segments, a plurality of output segments and an elongated transmission segment connecting the input segments to the output segments. The geometry of the buffer along with bridges located proximate to the transmitter modules eliminate the destructive effects of reflected waves set up by an unbalanced impedance combiner when one of the transmission modules becomes inope...

Communication of digital information between digital systems (2, 3) comprising clock generators (8, 9) is effected via storage in memory locations a1 to a8 and b1 to b8 of a cyclic buffer 4, in which, in succession, the information is written and read on a time base determined by the various clock generators (8, 9). Pointers stored in pointers (12, 13) determine the memory locations to be read out or written. If the pointers have become equal as a result of phase deviations of the clock generato...

Apparatus for measuring the pressure within a fluid-conveying member of a mixture of a fluid and particulate solids comprises an outlet port in the fluid-conveying member, a buffer vessel having walls defining a buffer volume for containing a buffer medium, the buffer vessel having first and second end portions, and having a measuring outlet at the first end portion being in fluid communication with the outlet port of the fluid-conveying member. An impulse conduit has its first end in fluid comm...

A buffer circuit provided with a transistor each on the input and output terminal sides, in which the transistor has been provided in order to keep constant a difference between a collector-emitter voltage of the input terminal side transistor and that of the output terminal side transistor.

An n-channel open drain or a p-channel open drain buffer circuit is disclosed. When the input to the buffer circuit changes to a disable state, the circuit once drives the output to the other potential level and then switches the output to a high impedance state. The buffer circuit reduces the period of time necessary for the output thereof to rise (in the case of an n-channel open drain scheme) or to fall (in the case of a p-channel open drain scheme) while making most of the advantages of an o...

The present invention is related an output buffer that has one input pin and produces a two-bit output. The input levels are a ground voltage, a supply voltage, and a voltage that is halfway between ground and supply. The invention is related to producing a minimal current when the input voltage is halfway between the ground voltage and the supply voltage.

A buffer device includes a plurality of latch stages which each have a latch device and a multiplexer. At least the multiplexer of the first latch stage on the output side is associated with a feedback loop of the latch device of this latch stage. The feedback loop is provided for data buffering. The buffer device keeps a data output on an output line stable.