A prescaler that operates in a broad band. The prescaler includes a buffer and a counter. The buffer includes a first amplification circuit, which has three inverter circuits of different drive capacities, a second amplification circuit, which has four series-connected inverter circuits, and a feedback circuit. One of the inverter circuits is connected between a capacitor and an inverter circuit via a first switch circuit and a second switch circuit. This varies the drive capacity of the first a...

The objective of the present invention is to present a buffer circuit by which a load can be driven at a high speed while restraining an increase in power consumption. A current input to npn transistor Q1 via node N1 is detected by current detection circuit 1. At bias control circuit 2, base voltage of npn transistor Q2 is regulated in such a manner that the current of npn transistor Q2 decreases in accordance with an increase in said detected current, and the current of npn transistor Q2 increa...

The present invention relates to a CMOS buffer circuit for liquid crystal display (LCD) drivers, which includes a single stage operational transconductance amplifier (OTA) with a differential of transistors for receiving a differential input voltage, a bias current source coupled to the differential pair and a single-ended output, the first bias current generating stage with a differential pair of transistors coupled to receive the differential input voltage to produce an output current in an ou...

A clock buffer has a band-pass frequency characteristic, in which a pass band of the buffer includes a fundamental frequency of a clock and a gain for attenuating signals, that is, a gain of less than 0 dB is provided at frequencies below the pass band.

Systems, devices, and methods, including logic and/or executable instructions are described in connection with a buffer circuit. One buffer circuit includes a flip-flop based first-in first-out (FIFO) buffer having an input and an output, selection logic coupled in series with the FIFO buffer input, and a random access memory (RAM) FIFO coupled in parallel with the selection logic. The selection logic diverts incoming data to the RAM FIFO after the FIFO buffer is filled to a first capacity level...

A buffer having a predetermined number, M, of input ports adapted for connection to one of a plurality of devices. The devices have different numbers, P, of ports, where P is less than, or equal to, M. The buffer includes a processor for determining the number of ports, P, of the one of the plurality of devices connected to the M ports of the buffer. The buffer couples the P ports of the device to M output ports of the buffer in a ratio of [M/P] sequences. A method for determining the number, P,...

A source-follower transistor based buffer provides high linearity. A replica transistor is used to generate a replica voltage substantially equal to the output voltage of the buffer. The replica voltage is level shifted by a level shift circuit and applied at the drain of the source-follower transistor to improve the linearity of the buffer. The buffer may be used in conjunction with a switched-capacitor sampling circuit. A damping circuit may be used to reduce charge glitches due to sampling. T...

A low-noise output buffer for a digital signal is based on an analog amplifier having bandwidth greater than the switching rate of the digital logic signal. A converter circuit converts the digital logic signal to a ramp signal provided as an input to the analog amplifier. The ramp signal has a slope determined by a bias current and an input capacitance of the analog amplifier. The bias current is generated by a bias circuit such that the bias current varies as the input capacitance of the analo...

A source-follower transistor based buffer provides high linearity. A replica transistor is used to generate a replica voltage substantially equal to the output voltage of the buffer. The replica voltage is level shifted by a level shift circuit and applied at the drain of the source-follower transistor to improve the linearity of the buffer. The buffer may be used in conjunction with a switched-capacitor sampling circuit. A damping circuit may be used to reduce charge glitches due to sampling. T...

An automated material handling system that includes an extractor/buffer apparatus capable of simultaneously accessing multiple Work-In-Process (WIP) parts, thereby providing a highly efficient interface between WIP storage locations and transport equipment. The extractor/buffer apparatus includes multiple extractor/buffer modules, each module being configured to interface with a location for holding WIP parts that is a number of WIP parts deep. Each module includes a platform for holding multipl...