A buffer circuit comprised of two matched stages is provided. The first stage develops a replica voltage that is used in the second stage as the input to a wide-band amplifier. The combination of the two feedback loops in the circuit result in improved linearity. The first amplifier dominates for moderate frequencies while the second amplifier takes over for high frequencies.

Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. In one implementation, a checkerboard buffer includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least two memory devices, each memory device having a plurality of memory locations, where d...

An input buffer comprises: a pull-up transistor connected between a power supply voltage and an input pad and having a gate to which a control voltage is applied, and a substrate to which a floating well voltage is applied; a transmission transistor having a gate to which the power supply voltage is applied and a substrate connected to a ground voltage, and transmitting a signal applied to the input pad; a buffer generating an input signal by buffering the signal applied to the transmission tran...

A computer system comprising a plurality of data processing elements connected through a shared communication bus to a memory so that for a given computer cycle at least one of the elements assumes control of the bus for accessing address in memory. The computer system having memory access circuitry connected between the data processing elements and memory which has first and second buffer units for storing prefetched bursts of data from the memory. The buffer circuit also having control logic f...

Described herein is a method for reassembling variable length packets from fixed length cells. When a variable length packet, for example, an Internet Protocol (IP) packet, is transmitted between routers over a link which transmits data as fixed length cells, for example, an asynchronous transfer mode (ATM) link, the packet must be segmented into compatible fixed length cells. The receiving router must reassemble the original packet from the cells as they arrive. A packet buffer free pool (300) ...

A direct memory access (DMA) first-in-first-out (FIFO) buffer includes two FIFO devices connected in parallel. An output multiplexer is controlled by a controller to pass to its output data provided by a selected one of the FIFO devices. Data is clocked into one FIFO device until it is full, after which data may be written from it. When data is written from a FIFO device, the FIFO device is emptied before data is again read into it. Using this arrangement, data can be read into one FIFO device w...

A buffer includes an input unit that inputs data; an output unit that outputs the data; a plurality of registers that stores the data while sequentially shifting the data from the input unit to the output unit; an output-data selecting unit that selects desired data from among the data stored based on a predetermined priority, extract the desired data from a corresponding register, and outputs the desired data to the output unit; a detecting unit that detects an error in the desired data; a diag...

A write-bank selecting unit selects different memory banks in response to N+1 consecutive write requests, respectively. In each memory cycle, a data writing unit inputs N or less write commands to a data access unit. On the other hand, a primary read-bank selecting unit selects readable memory banks in each memory cycle. A secondary read-bank selecting unit selects memory banks corresponding to read requests for which data blocks could not be read out in the preceding memory cycle. A data readin...

The present invention relates to a buffer device of the first-in-first-out type. The buffer device comprises a data inlet, a data outlet and a storage buffer. The buffer device also comprises an integrated circuit, which comprises an input buffer and an output buffer. An arrangement in the buffer device is used to combine the data inlet with the data out via either one of the buffers on the integrated circuit or via at least two of the buffers connected in series.

In some embodiments, a multichip package includes mounting pads to mount devices, such as integrated circuits, to a substrate, such as a printed circuit board, so that devices mutually placed on opposite surfaces of the substrate do not have interfering connections or connection vias. Other embodiments are described.