In a system having a first computer with a first processor, a reconfigurable bus for coupling the first processor to a first type of device in one configuration and to a second type of device in another configuration is accomplished using a bus coupled to the first processor and having at least a plurality of data and address lines and plurality of configuration lines, a device for detecting the assertion of a bit on one of the configuration lines, assertion indicating that a first type of devic...

The invention relates to a bus system comprising a first station and a second station coupled by a bus for transferring data and control signals. The bus is conceived to operate according to a protocol in which the first station repeatedly sends requests to said second station and the second station responds to the requests. The first station comprises an interruptible processor and a bus interface. The bus interface is operable to interrupt the interruptible processor upon reception of selected...

A method of creating a signal encoded with a message for transmission from a line unit to a switch unit in a network element of a communication network includes arranging in the message a plurality of contiguous bytes of traffic and arranging in the message a plurality of contiguous nibbles of signaling wherein there is one nibble of signaling for each byte of traffic.

A bus coupler for coupling transmitting and receiving stations to a two-conductor bus which feeds d-c current for coupling the on-board networks of the stations. It is designed for information traffic, for instance, with digital data transmission, for measuring and controlling and/or with analog signals for measuring and controlling and for speech transmission in that the information is superimposed as a completely symmetrical a-c voltage relative to a floating imaginary centralized ground, wher...

A bus connector comprising a base, an upper shell and a terminal unit, wherein said upper shell has resistor chambers for holding resistors from a bus and an elongated board at the front bottom edge thereof which is tightly pressed on the bus main track to which the connector is connected to seal off dust, and wherein said terminal unit has four terminals made in the same shape and respectively retained in four parallel grooves on the bottom edge of the base.

A clip operable to connect an electrical terminal post with a bus strip comprises: A. a channel section having opposed arms between which the bus strip is receivable, B. and a generally hook shaped section integral with one of said arms, said hook shaped section containing an opening to pass said terminal post extending generally parallel to said one arm, C. there being means on the channel section to retain the bus strip in a zone formed by the channel section.

A bus controller (20) for a data processing system, in which data is transferred between a bus master (10) and a bus slave (30) of a plurality of different data port sizes, is able to obtain port size information from an address signal using an incorporated address area/port size correspondence table (211), whereby a port size signal as a response signal from the bus slave is made unnecessary, thus simplifying the data processing system.

A bus device is used with a computer system. In the bus device, a bus-interfaced host performs data transmission in a first mode in response to a first command resulting from certain software execution of the computer system. A bridge device is coupled to and communicable with the bus-interfaced host via a first interface according to a first transmission protocol, and coupled to and communicable with the bus-interfaced device via a second interface according to a second transmission protocol. A...

A single bus apparatus enables the simultaneous execution of both high-speed data transfer, which requires real time operation, and low-speed data transfer. At least one of slaves I/F 22-0, 22-1, . . . that control slave devices SV0-SV3 upon the request from master devices MS0-MS3 connected to interconnection bus BS via master I/Fs 21-0 through 21-3 has a constitution made of multiport slave I/F 23 corresponding to a multi-access function that allows simultaneous access from plural master device...

An asynchronous bus for self-determined priority of communication among master computer devices communicating with slave devices through said bus where a multi bit data channel and a multi bit address channel are shared between all of said devices. A logic circuit in each said master device is connected to each of three signal lines common to all logic circuits in all of said master devices. One of the three lines is connected in series in the order of assigned priority between master devices. M...