A school bus invalid lift having a generally U-shaped lift member including a lift platform and a pair of upstanding lift frames within which the opposite sides of the lift member are arranged for vertical sliding movement. The lift members in each of the lift frames are interconnected by a chain and shaft system with the shaft mounted on the bottom of the lift member so as to equalize the lifting forces to prevent one side of the lift member from moving at a different speed than the other side ...

A plug-in bus duct comprised of a group of elongated generally flat busbars positioned in side-by-side relation inside an elongated housing, each busbar extending the length of the housing. Except in the plug-in section, only insulator sheets separate the busbars one from the other, and from the sides of the housing, thereby forming two side wall-insulator sheet-busbar `sandwich` sections separated by the plug-in section. In the plug-in section, the busbars are laterally spaced or offset one fro...

A loading and unloading system for a bus includes a generally flat platform upon which a person in a wheel chair can be moved into position from a sidewalk or roadway into the bus on the floor thereof or reverse. The bus has the usual air operated doors which open or close and permit use of conventional steps for normal movement of a passenger into the bus or departure from the bus. In order to accommodate a crippled or disabled person and particularly one in a wheel chair, a generally flat plat...

In a dynamoelectric machine, a non-segmented, continuous, direct current brush collector ring for energizing a rotating field may be up-rated by providing additional brushes to parts of the bus ring which, in the prior art, were considered inaccessible for servicing. The bus ring is rotatably supported by the dynamoelectric machine frame. Therefore, the bus ring may be turned clockwise or counterclockwise for servicing all parts of the bus ring especially those parts which were heretofore inacce...

A single parallel bus interconnects the various portions of a central processing unit. Data transmission between the various portions of the processor is based on sequential use of the common bus, and is synchronized by control circuitry. Circuit means are included for providing access of the various portions of the processor to the bus, and includes means for generating data on the bus for transmission, and for detecting data transmitted by the bus. To minimize access time to the bus whenever d...

A flexible strip bus bar for connecting a plurality of electrical contact posts, such as those found on a wire wrap board is disclosed. The invention comprises an elongated conducting strip of 0.008 berryllium copper, and has a number of biasing straps attached thereto for securing the strip and posts together. Preferably the straps are an integral part of the strips formed by pressing a portion of the face of the strip outwardly with a die. Insulation may be wrapped about any portion of the str...

A bus interface permits an upstream bandwidth and a downstream bandwidth to be separately selected. In one implementation a link control module forms a bidirectional link with another bus interface by separately configuring link widths of an upstream unidirectional sub-link and a downstream unidirectional sub-link.

A system and method for enhancing the performance of a parallel terminated bus. An implementation includes storing a minimum spacing for each transaction type in a memory, monitoring data transactions, performing a latch back operation if required, and executing a subsequent transaction following a prior transaction using a minimum spacing if the latch back operation does not occur.

This disclosure involves an on-chip bus architecture involving an on-chip bus that includes a collector node and at least one device node. Each device node is in communication with an on-chip device. The collector node is capable of conducting the multiple outstanding transactions with a plurality of on-chip devices over the on-chip bus wherein each on-chip device transmits all of its data signals across the on-chip bus in the form of packets. The on-chip bus includes at least one bus register, ...

A bus controller is provided including a processing means for performing processings of levels having cycle numbers which are different dependent on requesters which respectively issue an access request to a common memory. When it is expected from the present cycle number that a limit cycle number is exceeded, the bus controller selects a processing level with which the processing is performed with a smaller cycle number, or performs a control of giving no permission to a non-realtime bus access...