A non-conductive bus shroud for a dual circuit breaker system that has a plurality of vertical walls extending generally perpendicular from the top side and including at least one bus member support vertical wall. The dual circuit breaker system includes a housing assembly having a back wall, a first circuit breaker having at least one protruding line terminal, a second circuit breaker having at least one protruding line terminal and at least one bus member extending between the at least one fir...

An electrical bus bar is disclosed which is formed of two parallel bars that lie together in juxtaposition in parallel planes except where conformations in one or both bars result in their separation to form a region into which a connector pin can be inserted. A means is provided for holding the two bars of the bus bar together so that they grip the connector pin after the pin is inserted into the connection position. Several means are disclosed for holding the bars together. The preferred means...

A bus loader for a wheel chair and for the infirm embodies a platform which is mounted within the entrance area at the front of the bus. A minimum change in the standard bus is achieved by removing the bottom and intermediate steps at the front entrance and mounting the loading mechanism within the resulting recess. The loading mechanism is so constructed that the doors will swing in at each side of the opening in a manner in which they are normally operated. The platform is moved to the ground ...

A bus controller for a computer system. The controller comprises a monitor for monitoring request signals and response signals between a first component and a second component each connected to a bus of the computer system; and a terminator controlled by the monitor to terminate a request from one of the first and second components if a response to the request has not issued within a predetermined period of time.

Disclosed is a bus system, which can rapidly perform various operations, that has a configuration wherein master and slave core circuits are connected to a system bus through master and slave I/F circuits.According to the present invention, since master and slave I/F circuits perform part of the processing required for data communication between master and slave core circuits, the processing speed can be increased, while the amount of data to be exchanged by the master and slave I/F circuits and...

A bus has two power consumption modes. A variable bus termination impedance is controlled to provide different bus termination impedances. A controller is coupled to the bus and includes a variable clock having different frequencies that are selectively provided to the controller. The impedance is increased or decreased responsive to the frequency being provided to the controller.

The invention relates to a bus system comprising a first station and a second station coupled by a bus for transferring data and control signals. The bus is conceived to operate according to a protocol in which the first station repeatedly sends requests to the second station. The first station comprises a processor, a bus interface, and a buffer coupled to said interruptible processor and said bus interface, the processor being operable to generate request properties for the requests to be sent...

A bus interface is described, in particular in motor vehicles, for connecting a bus device to a bus using a pair of complementary bus lines, including a first driver circuit whose input is connected to the bus device and whose output is connected to the first bus line of the pair of complementary bus lines, and a second driver circuit, which is complementary to the first driver circuit and whose output is connected to the second bus line of the pair of complementary bus lines, the input of the s...

The invention relates to a bus system comprising a first station (202) and a second station (203), (204), coupled by a bus for transferring messages, said bus being designed to operate in accordance with a protocol in which said first station (202) periodically sends messages in a predetermined order to the second station (203), (204), wherein said first station (202) comprises an interruptible processor (206), a memory element (208) comprising a buffer (501, 502), and a bus interface (207), whe...

An electrical distribution switchboard including a multiphase horizontal main bus and a multiphase vertical riser bus. Each individual horizontal phase conductor comprises a plurality of spaced parallel bars connected to the corresponding individual vertical phase conductor through an extruded aluminum block having a plurality of grooves formed in each side to receive the spaced parallel bars. The bars are welded in the grooves and the connector welded to the individual vertical phase conductor.