A computer system includes a main memory and a cache memory arrangement, wherein a cache memory unit is associated with each of the several CPU's in the system. Each cache responds to the virtual address signals issued by the associated CPU, in parallel with a mapper unit which, in turn, converts the virtual address signals to physical address signals for addressing the main memory. The cache is subdivided into subunits each responding to a particular program of a multiprogram CPU. When any of t...

A cache or holder for a key or other small item comprises a first part having at least one pocket for holding a key and a second part releasably securable to the first part and having an adhesive layer or other securing device for securing the second part to a selected surface in a concealed location.

In a data processing system having a host processor, a cache store for storing segments of data, a bulk memory and a storage control unit for controlling transfers between the processor, cache store and bulk memory, the storage control unit normally responds to a read or write command from the host processor to control the transfer of data. If a copy of the data transferred is not resident in the cache store then a copy is written therein by the storage control unit. If the length of a data tran...

A set associative type cache memory incorporated in a microprocessor includes memory arrays arranged in a group for each line, and only a memory array selected by a line address selected at the time of operation is made operative, thus reducing power consumption.

An input/output system includes a local memory module including a cache store and a backing store. The system includes a plurality of command modules and a system interface unit having a plurality of ports, each connected to a different one of the command modules and to the local memory module. The cache store provides fast access to blocks of information previously fetched from the backing store in response to memory commands generated by any one of a plurality of command modules during both da...

The disclosure provides a plurality of embodiments for controlling the bus paths for a line of data from any cache in a multiprocessing system (MP) to any requesting cache or I/O channel processor in the MP. The data transfers can occur in parallel among plural CPU caches, channel processors and main storage (MS) sections using crosspoint switches in a manner which utilizes the high circuit count of LSI modules without substantially utilizing the module I/O pin count to enable MP structures to c...

A cache unit includes a cache store organized into a number of levels to provide a fast access to instructions and data words. Directory circuits, associated with the cache store, contain address information identifying those instructions and data words stored in the cache store. The cache unit has at least one instruction register for storing address and level signals for specifying the location of the next instruction to be fetched and transferred to the processing unit. Replacement circuits a...

A method of setting a memory array to a common logic value by activating all the line switches by the precharge device for the duration of a word signal and simultaneously applying the common logic value directly to all the bit lines.

A method for Direct (DASD) cache management that reduces the volume of data transfer between DASD and cache while avoiding the complexity of managing variable length records in the cache. This is achieved by always choosing the starting point for staging a record to be at the start of the missing record and, at the same time, allocating and managing cache space in fixed length blocks. The method steps require staging records, starting with the requested record and continuing until either the cac...

In response to a command including file extent information defining a file area received from a host processor, a disk cache processor stores the file extent information in an extent table and reserves a corresponding area in a disk cache buffer. In response to a WRITE command, the processor stores the data in the corresponding reserved area of the disk cache buffer and sets a write flag of the corresponding entry of a cache directory. When the processor is idling, it writes to a disk unit the d...