Disclosed is a data processing system including virtual-addressed and real-addressed stores. One store is addressed with real addresses and the other store is addressed with virtual addresses. Whenever an addressed location is to be accessed in a store addressed by the other type of addresses, the address is translated to the other type of address. If a virtual address cannot access the desired location in the virtual store, the virtual address through a virtual-to-real translator is translated ...

The cache reload time in small computer systems is improved by using a distributed cache located on the memory chips. The large bandwidth between the main memory and cache is the usual on-chip interconnecting lines which avoids pin input/output problems. This distributed cache is achieved by the use of communicating random access memory chips of the type incorporating a primary port (10) and a secondary port (14). Ideally, the primary and secondary ports can run totally independently of each oth...

A cache system having a plurality of read-in ports through which data fetched from a main memory system can be transferred regardless of the type of the data fetch request. Further, each data fetch request is output from an available read-in port, during the data fetch operation for a previous data fetch request of the same type.

When a processor issues a read or write command to read one or more words from a disk, a cache store is checked to see if a copy of the segment(s) containing the word(s) are present therein. If a copy of the segment is not present in the cache store then it is moved from disk to the cache store and sent to the processor. A segment descriptor table is maintained and the entries in the table are linked by forward and backward age links. When a segment is brought into the cache store from a disk be...

The disclosure enables concurrent access to a cache by main storage and a processor by means of a cache control which provides two cache access timing cycles during each processor storage request cycle. The cache is accessible to the processor during one of the cache timing cycles and is accessible to main storage during the other cache timing cycle. No alternately accessible modules, buffering, delay, or interruption is provided for main storage line transfers to the cache.

A data processing system includes a plurality of system units all connected in common to a system bus. Included are a main memory system and a high speed buffer or cache store. System units communicate with each other over the system bus. Apparatus in the cache store monitors each communication between system units to determine if it is a communication from a system unit to main memory which will update a word location in main memory. If that word location is also stored in cache then the word l...

A multiprocessor system is described in which a plurality of central processor units share the same main memory over a common asynchronous bus. Each central processor directs all memory requests to its own high speed cache memory. If the request is to read data from memory, the cache memory control determines if the addressed data is present in the cache memory. If so, the data is transferred to the processor without accessing main memory over the bus. If the data is not present in the cache mem...

Block information from a main memory, which is registered in an address register, is applied to a directory. A bank address in the main memory is taken out from the respective locations defined by the block information in each bank of the directory. A comparator compares the bank address with a bank address of the main memory registered in said address register. The output signal from the comparator is applied as a control signal to a control ROM. The directory memory applies an address signal t...

In a processor system with a virtual memory organization and a cache memory table storing the physical addresses corresponding to the most-recenty used virtual addresses, access to the cache table is enhanced by associating upper and lower MSB portions of a virtual address with corresponding upper and lower portions of an associated cache address. The separate cache address portions are placed in separate cache address storage devices. Each cache address storage device is addressed by respective...

A simplified cache with automatic updating for use in a memory system. The cache and the main memory receive data from a common input, and when a memory write operation is performed on data stored at a memory location for which there is a corresponding cache location, the data is written simultaneously to the cache and to the main memory. Since a cache location coresponding to a memory location always contains a copy of the data at the memory location, there is no need for dirty bits or valid bi...