An integrated circuit sensor circuit (10) is disclosed which is operable in differential or single-ended modes at DC input potentials which can be below the integrated circuit substrate bias potential (ground). Substrate injection is prevented and the circuit is operable for input signals which can vary relatively widely with respect to the substrate bias potential. This is accomplished even though only a single polarity power supply (+5 volts) with respect to substrate bias potential is used fo...

Arrangement for arcless interruption of a-c load current in response to a current interruption command. Separable contact means serially connected with controlled impedance means, and parallel connected diversion means are intermediate the a-c source and the load. The controlled impedance comprises field effect transistors (FETs). Since FETs usually have only a single inherent junction, at least a pair of the FETs are oppositely poled so that load current can be cut off notwithstanding the direc...

A driver circuit for use in a circuit board tester performs both functional and in-circuit tests on a given device under test (DUT). The tester provides a control signal representative of a command for the driver circuit to provide test signals to the DUT. The driver circuit incorporates two stages: a pre-driver stage and a driver stage. The pre-driver stage consists of an amplifier connected to fast switching transistors with the ability to move in and out of saturation rapidly. The amplifier r...

A control circuit is provided for a circuit interrupter that achieves an inverse-time characteristic for overcurrents that include instantaneous current levels higher than the interrupting capability of the circuit interrupter by synchronizing the operation of the circuit interrupter to ensure that circuit interruption takes place when the instantaneous current is within the interrupting capability of the circuit interrupter. This interrupting capability is similar to let-through current and is ...

An integrated circuit protection device for use with a voltage regulator used to drive an integrated circuit to prevent damage to the integrated circuit which goes into a "latch up" condition. The integrated circuit protection device comprises a first switching circuit, connected to the output of the voltage regulator for selectively connecting the output of the voltage regulator to ground and a second switching circuit, connected to the input and the output of the voltage regulator and to the f...

A control circuit is provided for applying energy to operate a circuit interrupter in response to, and a selected time after, the onset of overcurrent in an alternating-current line. The control circuit includes a transducer for producing output current proportional to the current in the line. The power supply includes an energy storage circuit that stores energy derived from the output current. The stored energy, which is maintained within a first range when there is no overcurrent in the line,...

A control circuit is provided for operating a circuit interrupter in response to overcurrent in an alternating-current line in which the circuit interrupter is located. The control circuit includes a transducer for producing output current proportional to the current in the line. A time-current trip signal generator circuit responds to output current representative of moderate overcurrent in the line by producing a trip signal after the passage of a time period that is inversely related to the o...

A protection circuit for a semiconductor circuit for protecting it from a thunder surge and overcurrent or overvoltage. A surge absorbing element and a Zenor diode are in parallel connected to the semiconductor circuit. A first fuse are connected before between the electric source and the surge absorbing element. A second fuse and a resistor, which is in series connection, is arranged between the surge absorbing element and the Zenor diode.

A protecting circuit is disclosed, that comprises a static electricity protecting means composed of a plurality of p channel type transistors, wherein a source electrode, a gate electrode, and a substrate electrode of a first p channel type transistor are connected to a high voltage power supply terminal, a drain electrode of a second p channel type MOS transistor being connected to a low voltage power supply terminal, a substrate electrode of the second p channel type substrate being connected ...

Since the logic levels on both edge sides (node n1 and node n2) of an NMOS connected to a word line are set to the same level corresponding to the logic level of the chip enable signal, even in a memory having an MOS transistor with a short gate length due to an increase of the storage capacity, a leak voltage can be prevented from taking place in the chip standby state.