Transistors Q11 and Q12 constitute a first differential amplifier, their emitters are connected with each other by a resistor R1 and also connected respectively to constant-current sources CS11 and CS12. Transistors Q15 to Q17 constitute a second differential amplifier, and the collector of the transistor Q16 is connected with a current mirror 17. This current mirror circuit 17 is constituted by transistors Q18 and Q19 and resistors R3 and R4. The capacitor 22 is supplied with a current from the...

An object of the present invention is to provide a buffer circuit little sensitive to a deviation from a threshold voltage of each of transistors. In order to achieve the above object, the present invention provides a typical buffer circuit comprising the following components. Namely, the buffer circuit comprises a first transistor having a first terminal connected to a current source, a second terminal connected to a first node and a control electrode connected to a first input terminal; a seco...

An integrated circuit has an analog output circuit for outputting an analog signal and a leadless terminal for connecting an output line of the analog output circuit to a circuit board by soldering, and measures and transfers an analog output voltage of the leadless terminal in a state in which it is mounted on the circuit board. A measuring unit has a switching unit for connecting the analog output circuit to the measuring unit upon failure diagnosis, and an AD converter for measuring the analo...

A switch circuit includes a balanced line connected between one end of an unbalanced line having another end connected to an input terminal and an output terminal and a balanced line connected between the one end of the unbalanced line and an output terminal. On each of the balanced lines, a plurality of quarter-wave transmission lines are connected in cascade, and each of a plurality of FETs, whose impedance is controllable, is connected between one pair of transmission lines constituting a bal...

In a first direct-sequence spread spectrum communication system having a transmission circuit where a data signal to be transmitted is coded by a first chip code signal and a receiving circuit for decoding the transmitted data signal with a second chip code signal, the synchronization between the said first and second chip code signals is performed when an asynchronous condition of said first and second chip code signals is detected over a predetermined interval. In a second direct-sequence spre...

A reset circuit of a semiconductor circuit for reliably resetting plural reset target circuits in the semiconductor circuit, even when a surge noise signal having a short pulse length or the like is input to the reset circuit, the reset circuit including a reset signal control circuit for controlling timing of deactivating a reset instruction signal for resetting plural reset target circuits in the semiconductor circuit. Respective reset target circuits are for outputting reset completion signal...

In a circuit board comprising multiple layers and having an integrated circuit mounted on the outer layer thereof, a main power supply plane and a sub-power supply plane, which is disposed in an island fashion with a clearance that terminates electric connection with the main power supply plane, are formed on the same layer. The main power supply plane and the sub-power supply plane are connected by first power supply patterns that are formed on a layer different from the layer on which the powe...

Test circuit for testing a circuit to be tested, having a test data generator, which generates test data in a manner dependent on data control signals which are received via data control lines from an external test unit, a data output driver for outputting the generated test data via data line pairs of a differential data bus to the circuit to be tested, a data input circuit for receiving data that are read from the circuit to be tested and transmitted via the data line pairs of the differential...

A chip capacitor is arranged on a microstrip conductor forming a microstrip line. The chip capacitor has a dielectric material and electrodes provided on both ends thereof. The electrodes of the chip capacitor are connected to the microstrip conductor. A resonance frequency is decided by the length of the microstrip conductor between the electrodes of the chip capacitor, the dielectric constant and the thickness of the dielectric substrate and the capacitance value of the chip capacitor.

The present invention provides a bar circuit for reducing cross talk and eddy current of an integrated circuit. The bar circuit comprises a semiconductor substrate with a first conductivity type; a strip of first well with a second conductivity type in the semiconductor substrate; and a strip of second well with the second conductivity type in the semiconductor substrate. The strip of second well is located below and adjacent to the strip of first well, whereby forms a junction barrier for reduc...